Pipeline Architecture And Parameterization Design Of ASIP

Application Specific Instruction set Processor (ASIP) has been proved to be a success in the field of large-scale digital signal processing, it has met all the requirements of our lab project research. Now, in order to satisfy the need of real-time processing in even larger scale digital signal processing, the performance of the ASIP should be enhanced. We adopt pipelined structure instead of former one-instruction per cycle model and divide four stages of the pipelined architecture based on the features of the instruction set and FPGA hardware platform. Meanwhile, we use techniques such as forward path to solve the problems of data dependency and control dependency, so that the pipeline can perform more efficiently. After simulating and verifying the design by related EDA software, it is proved that the pipelined architecture of ASIP can run 120-percent faster at cost of 20-percent more resource consumption, which means that the design has reached the expected goal.Moreover, we have researched the parameterization design of ASIP and designed a parameter-configurable platform, on which users can set the parameters according to their needs, so that the hardware resource cost and power consumption can be minimized.