Design And Implementation Of Error Control System For High Data Rate Transmissons

With the fast increasing information capacity and data rate requirement, the resource of power and bandwidth within satellite high data rate transmissions is becoming more and more tight. Power and bandwidth-efficient coding technology is a guarantee of data transmission with high rate and low bit error rate. The key for error control technology of high data rate transmissions is how to implement a encoder/decoder with high speed and high performance simultaneously.The performance of TCM code is analyzed in the thesis, and a high rate concatenated coding scheme is presented using bandwidth efficient TCM inner code and RS outer code.After the encoding/decoding algorithm of RS code is stated, a RS decoding scheme with pipeline architecture is brought forward, meanwhile the syndrome calculator and Chien search unit which consume much time is optimized. By the definition of semi-ring concept, the traditional one step add-compare-select operation of Viterbi algorithm is turned into M step add-compare-select operation, which overcomes the bottleneck effect of the traditional operation. An add-compare-select unit of four stage pipeline architecture and a parallel survivor memory unit based on register/three-state-gate trace back algorithm, which consist of the whole high speed Viterbi decoder whose decoding rate is four times faster than that of traditional Viterbi decoder, are designed and implemented on FPGA.