The Implementation Of Serial-Parallel Combined Viterbi Decoder In FPGA

Convolutional code is widely used in wireless communication systems while the Viterbi algorithm is the near-optimal decoding scheme for it. With the development of FPGA chips, the processing ability and the flexibility in the design are greatly improved, it is an excellent way to implementing the Viterbi decoder of a communication system in FPGA chips.According to the analyzing result of Viterbi decode algorithm, this paper designs and implements a soft-decision Viterbi decoder. The decoder has introduced a Serial-Parallel combined architecture; compare with the parallel way, this design can use less chip resource to achieve the decoding rate. In order to simplify the logic circuit of the control module and optimization the system, this paper proposes a new architecture to store the path metric. This paper introduces the track back processing to get the decode results, it saves register resources and has fewer power consunptioa The decoder designed in this paper can finish the decode operation to two streams of data which rate is variable. It balances the consumption of resource with the throughput capacity, the decode core can be used in other communication systems.This paper implements the Viterbi decoder with Verilog HDL in the Xilinx ISE integrated development environment. During the implement, we use pipeline to increase the operation efficiency, and verify it by simulating. The Viterbi decoder also achieved the design requirements in the performance test...