Fpga Implementation Of Viterbi Decoder

In modern communication, Error-Correcting codes are often used to improve the system performance, among which the convolutional code is widely adopted because of its excellent capability. The Viterbi algorithm is a probability-decoding algorithm of convolutional code, and it's a maximum likelihood decoding procedure in essence. In practical application, how to realize the Viterbi decoder effectively to satisfy the actual demands is important. In the paper, it firstly introduces the basics of the convolutional code and the Viterbi algorithm; then explains in details the FPGA realization of each module of Viterbi decoder, and mainly emphasizes the two key units of decoder: Add Compare Select unit and Path Metric Memory unit, and compares the nowadays commonly implemented realization method. Finally the Viterbi decoder implements the simulation via Modelsim and realizes in the FPGA platform of Xilinx.