Research On The System Architecture Of Video Decoding Chip

With the development of VLSI design, more and more transistors are integrated into one chip. At the same time, the emphasis of VLSI design is not limited to transistor level, gate level, and function module level any more, but transferred to system level, namely System on Chip (SoC). These design techniques are the main areas of interest in nowadays VLSI design.When the research on SoC goes deeper, some new problems appear, and the solutions that urgently needed become the hottest area in nowadays IC design. These include: IP (Intelligence Property) development and utilization, hardware/software co-design, low power design and design for testability, etc.The work of this dissertation concentrates on design an IP core for ISO11496-2 real-time decoding. Based on this work, two goals are expected: first, in the filed of SoC design, we have discussed the methodology of design description language and BOC (Bus On Chip). Second, in the field video signal decompression, we have done researches on specific algorithm, followed by the design of a decoder for ASP@MPEG-4. Besides, this architecture can be used for other video signal decompression because the commonness of video decompression has been taken into consideration in the design.The dissertation has two parts. The first is about SoC design. The general problems met in SoC design are introduced first, and then the SystemC language is discussed from the aspects of structure, simulation and design flow.The second part of the dissertation is about the design of ASP@MPEG-4 video decoder. The IP structure is introduced first, and our design emphasis will be on data structure and bus schedule.