| As the technological level of LSI and VLSI steadily development, the scale and the complexity of digital system are expanded at very high speed. So, it is very important meanings to offer a kind of fast and high-efficient logic simulation system for designing and making the digital system..People mostly adopt VHDL language in designing and simulation digital system. But the huge scale of design and the language complexity of itself lead to the problems of difficult developing, slowly run speed and heavily taking space of the simulator. The speed of simulator depends on the simulation algorithm and executive technique. On base of the view of time and space, people proposed lots of software and hardware method, which improved the speed of simulation from different level and solved some problem existed in simulation system. This paper mainly introduce distribution and parallel VHDL simulation which use lots of processors to parallel simulate VHDL model circuit according to the parallel characteristic of circuit itself. So this method can greatly improve simulation speed. However, further research is needed.This paper puts forward a parallel simulation algorithm combining a local network and PVM parallel software. Itpartitions the circuit into a lot of IPs by using the way of first dividing after sorting, then orders nodes of one LP according to the circuit relationship. Sorting algorithm can solve logic gate circuit for more fanout, more loop nestification and feedback alternately. We sort these nodes according to their joint relationship by the sort algorithm that can determine the priority order of digital circuit simulation and give the feedback chain. The sorting algorithm can prevent unordered simulation that lead to waste time, which improved the speed of simulation to a certain extent. The synchronism between the workstations can reduce certain expenses through conservative method. Analysis indicates this kind of parallel method can greatly improve simulation time of VHDL.
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