Study Of Parallel Simulation Algorithm For Digital System

With the increase of integration and the complexity of the designing of VLSI, a very high-speed parallel simulator that can simulate the integrated circuits described by VHDL is required. Therefore, this thesis proposes a parallel simulation algorithm for a simulator based on COW.In the thesis, it is summarized the development and the characters of VHDL that is a widely used standard hardware description language, and introduced common simulation algorithm, parallel computing hardware and the software-MPI. It is also presented the basic structure of parallel simulation algorithm, that is, establishment, partition, communication and synchronization. Based on them an algorithm of parallel digital system simulation is put forward. The algorithm adds sorting function, uses high efficient partition strategies and a new data storage model, improves Time Warp algorithm and LP's sending-receiving mechanism. After analyzed the algorithm, the consequence indicates that the algorithm makes the simulator could adequately use a variety of resources and possess high efficiency.The algorithm is realized by OOD under the environment of COW, windows and MPI. LP, Node, Communicator, VirtualTime, signal and Event are designed and realized. Especially, LP, Node and Communicator are described in detail. Those are the bases of the parallel simulation algorithm. Finally, in the thesis, there arethree-group-data to gate-level circuits. The scales of them are {100, 200, 400, 800}, {1000, 2000, 4000, 8000} and {10000, 20000, 40000, 80000}, and these data are tested in COW with 4 LPs and 8 LPs separately. The consequence accord with the algorithm theory, that is to say the algorithm is competence for parallel simulation. Moreover, OOD is used in the realization of the algorithm, which makes the simulator easily to extending for the future.