Design of CMOS adaptive-supply serial links

There is a need for IC chips that can support very high input/output (I/O) bandwidths. The key to high bandwidth is high per-pin I/O data rate and low power operation to enable a large number of pins to be integrated. This dissertation explores how adaptive power-supply regulation and parallelism can help minimize the link power dissipation while achieving high performance.; To maximize the energy-efficiency, the supply voltage is adaptively regulated to the minimum required for the desired frequency. The adaptive supply uses a buck regulator for efficient voltage step-down, and this regulator uses a novel digital sliding controller that monitors the link performance and adapts the voltage to process and temperature variations. Since the dynamics of the sliding controller do not depend on its operating frequency, the controller can be operated off of the adaptive supply, achieving the overall efficiency of 89--95% over the entire operating range (over 40x change in power).; The analog sections of the I/O circuits are modified to extend their operation to very low voltages. The input signals to the transmitter output stage are level-shifted to make the effective threshold voltage of the output devices zero and to mitigate the output current vanishing as the supply voltage approaches Vth. The receiver stage uses an integrating stage with no sampling switches and a charge-injection-based comparator that can operate at very low supply. Overall, the link is operational down to 0.9V with Vth of 0.55V.; The timing for the links is controlled by either PLL or DLL circuitry that locally generates the needed multiphase clocks for the parallelized transceiver architecture. The area of these circuits are reduced by using the adaptive supply as the global loop to coarse-tune the frequency and using the local loops to fine-tune over a narrow range. In this architecture, the PLL design requires 52% less power and 41% less area than the DLL design with about the same jitter. The clock recovery PLLs use bangbang control and its nonlinear effects are carefully analyzed.; Prototype chips were fabricated in a 0.25mum CMOS technology. The adaptive-supply link operates from 0.65 to 5.0Gb/s. At 3.1Gb/s, the complete link dissipates only 113mW.