Research On The Binarized MLP Network Based On The Memristor Crosspoint Array

Considering the memristor crossbar architecture has the natural characteristic of accelerating weighted sum caculation,and the memristor device itself has excellent nonvolatile storage performance and multi-valued adjustability like synapse,the memristor array based neuromorphic processor is expected to break the“von Neumann bottleneck”of the traditional computer architecture and provide hardware support for the efficient implementation of artificial intelligence in the post-Moore era.However,for the state of the art technology,the realistic memristive devices reported in literature exhibit many nonideal properties,such as nonlinearity,variation,limited precision,and finite ON/OFF ratio.There is a big gap between the real devices and ideal synapse devices.In particular,the nonlinearity of the device limits the accurate adjustablility of synaptic weights,which in turn decrease the recognition accuracy for the neural network applications.On the other hand,3D integration technology is one of the important methods for memristors to realize ultra-high density integration,and provides a technical basis for the application of memristors on large-scale neural network.However,the traditional circuit model of 3D array requires huge simulation resources.As a result,it cannot be used for simulating the large-scale(such as megabits)arrays,which limits the development of memristor based3 D arrays for the large-scale neural network applications.This article aims to design binary memristor array based MLP neural network with high recognition accuracy.The main contents of this dissertation include:Chapter 2 gives a thorough literature review of two important memristor integrated array and MLP network principles.First,the basic structure,read-write strategy,and equivalent circuit model of the memristor 2D array are reviewed(Section 2.1).Subsquently,a review of the basic structure,read-write strategy,and the traditional equivalent circuit model of the memristor 3D array is given(Section 2.2),and we also give a brief analysis of the problems existing in the traditional model.Then,a review of current research on MLP networks(Section 2.3)is also summarized.In Chapter 3,the design of a binary MLP network based on a 2D array of memristors is stuyded,and we propose a binary MLP recognition network based on a memristor 2D array.First,the overall design of the binary MLP network based on the memristor 2D array is described(Section 3.1).Then,the key technologies in network design were discussed,including the design of hidden layer size,the design of array operations,and the weight coding strategy(Section 3.2).Finally,the simulation verifies the feasibility of studying the read and write operations of the memristor 2D array for binarized MLP networks,analyzes the delay,power consumption and occupied area of the design in the array operation,and discusses the recognition accuracy of the MLP network under the device with the nonideal factors(Section 3.4)..In Chapter 4,the memristor 3D array modeling and proposes a simplified model of the memristor 3D array is studyed.Firstly,based on the structure of the memristor 3D array,the data storage mode of the memristor 3D array is analyzed.The circuit nodes that can be simplified by the traditional model are deduced and the complexity of the traditional model is reduced(Section 4.1).Then,verify the accuracy of the read and write operations of the simplified model,and also evaluate the performance advantages of the simplified model(Section 4.2).Finally,based on the proposed simplified model,the influence of various parameters on the performance of the memristor 3D array is also studied(Section4.3).In Chapter 5,the design of binary MLP network based on memristor 3D array is stuyded and we propose a binary MLP online learning network based on memristor 3D array.First,the overall design of a binary MLP network based on a memristor 3D array is described(Section 5.1).Then,the key technologies in network design are discussed,including the design of hidden layer size,the design of array operations,and the weight coding strategy(Section 5.2).Finally,the simulation verifies the feasibility of studying the read and write operations of the memristor 3D array for the binarized MLP network,analyzes the delay,power consumption and occupied area of the design in the array operation,and discusses the device non-The effect of ideal factors on the recognition rate of the network(Section 5.3).