Research And Implementation Of Simulation Environment For Thread Level Parallelization On Multi-core Architecture

Multi-core/Many-core architectures have already become the first choice for current high performance general purpose processor design. With the development of manufactory technology, more and more computing resources and storage resources are integrated into processor chips, which makes it possible to exploit coarse-grained parallelism via speculative parallelization techniques. A lot of researches have indicated that speculative parallelization can simplify parallel programming model and improve the performance of applications.Software simulation is always used as a main method when studying processor architecture. It also plays an important role in current multi-core/many-core processor architecture research. A lot researches are performed based on software simulation tools, especially when the research work is limited by time and costs. However, slow simulation speed is an outstanding shortcoming of software simulation tools.To support study on speculative parallelization, this paper focuses on how to design and implement an efficient software multi-core/many-core simulator which can support thread level speculation. The main work and achievement of this paper includes:1. Design and implementation of TLS Simulation Library(TLS-SL)Based on the analysis of current thread level speculation mechanisms and corresponding multi-core/many-core architectures, we proposed a TLS Simulation Library(TLS-SL), which has been implemented on open-source SESC software simulator and its correctness has also been verified.2. Post-Execution Timing Analysis(PETA)To solve the inefficiency problem of software simulator, this paper studies the acceleration method of SESC simulator. A parallel simulation method, PETA(Post-Execution Timing Analysis), is proposed. Based on PETA, a parallel SESC simulator named PETA-sim is implemented. Experimental results oriented Parsec benchmark suite on Intel multi-core platforms indicate the correctness and effectiveness of our method.Our work can provide great support for researches on thread level speculation mechanisms on multi-core/many-core platforms.