Path Delay Fault Testing For Arithmetic Circuits

Delay fault test is researched for arithmetic circuits in this thesis. With the rapid development of semiconductor technolology, the integration degree and the operation speed are increasing which lead to delay fault test becoming increasingly critical. The Arithmetic circuits which include adders and multiplies are widely used in many domains such as signal processing. In the past, much attention has been paid to stuck-at fault test and little research has been reported on the delay fault test for these circuits. Due to high reliability and performance requirement, the existing of delay fault can not only affect the perfermance, but also develop to be potentially fatal damage. The high integrtion and high speed operation can cause them to be much easily suffered from the delay faults. So, investigation of delay fault test for these circuits is very significant.The contents of the thesis include algorithm detail of delay fault test generator, delay fault test of adders, multipliers, modular arithmetic circuits, etc. The main contributions of this thesis are summarized as follows:1. The algorithm and design detail of delay fault test pattern generator based on accumulator is investigated. As accumulators are commonly available in arithmetic circuits, the reusing of these devices as test pattern generators can not only reduce hardware cost, but also avoid the performance degradation. The proposed scheme can suit well to those high integration and hardware space limited circuits such as arithmetic circuits. The algorithm and design detail is covered and the comparison to related work shows that the proposed scheme has low hardware overhead and low time cost.2. The delay fault tests of conditional sum adders and parallel-prefix tree-like adders are addressed. These two kinds of high-speed adders are commonly used for their highly regular structures and easy implementation in VLSI. A design-for-testability scheme is presented for conditional sum adders with low hardware cost and low size of test set which can guarantee single-path sensitizable testability by exploiting their structural property and parallel testing. This is the strictest requirement for path delay fault test and can guarantee the system performance. Furthermore, a learning-based test strategy is proposed which can generate all the needed test vectors for conditional sum adders with any input bits and can improve the test efficiency by reducing test complexity and test time. Based on exploiting of inherent structures, the path delay fault testability of the parallel-prefix tree-like adders is analyzed. The results demonstrate that all the paths in the parallel-prefix tree-like adders can be guaranteed single-path sensitizable testability. In addition, a path selection method is proposed in which a minimal subset of paths is selected and there is no requirement for all the paths to be tested. As a result, the test time is much reduced. The test efficiency is also improved.3. The path delay fault test of array multipliers is researched. Based on analysis of path delay fault testability and sensitizable condition of key paths, a built-in self-test scheme is presented for the delay fault test of array multipliers in which an accumulator is reused to generate a kind of single-input-change sequences as test patterns. Such kind of single-input-change sequences has been designated to be more effective than multiple-input-change sequences when highly robust delay fault coverage is targeted. The proposed scheme is well balanced between the fault coverage and the number of test patterns. Simulation results show the scheme has merit of high delay fault coverage with low hardware cost and small number of test.4. The path delay fault test of modular arithmetic circuits is targeted. Based on exploitation of design tendency to be hierarchical and modular for modern arithmetic circuits, a satisfiability-based path delay test scheme is proposed. In such scheme, a hierarchical path delay fault test method and a modular functional delay fault test method are researched respectively. During the realization process, a series of optimization algorithms is proposed which makes such scheme suit well to modular and regular arithmetic circuits and the comparison to related work shows that the proposed scheme can much reduce test time.