Research On Test Generation Algorithm For Delay Fault And I_DDT Test Experiment

With the rapid development of the designing and machining technology of IC , testing becomes more and more difficult. It is considered to be a very important part in IC industry. Especially after IC industry entering deep submicron stage of development, by integrating many kinds of IP core, the function of SOC becomes stronger and stronger, but the rapid development also brings in a series of problems.Voltage based testing and quiescent power supply current testing are typical test methods for digital CMOS ICs. Voltage based testing can detect many defects in a simple and fast way. it is effective in detecting stuck-at fault, but a little deficient in detecting other types of faults for CMOS ICs. In the early 1980's, quiescent power supply current testing method was proposed for CMOS testing. However, with the development of deep submicron designs, the limitations of this method, such as slow testing rate, small difference between faulty circuits and fault-free circuits, also become apparent.In order to improve the fault coverage, the dynamic current testing was proposed in the middle 1990's. By analyzing the changing process of transient current between two steady statuses of faulty circuits and fault-free circuits, it can detect some faults that cannot be detected by other testing methods. Based on the existent I_DDT testing algorithm, a test generation algorithm for gate delay faults is presented, having three test patterns. The experimental results show that the algorithm is effective.To further validate the theories of I_DDT testing, the I_DDT of real circuits is measured. Given a C432 circuit with three special faults: stuck-open fault in node 168, s-a-1 fault in node 444 and delay fault in node 264, the faults are tried to be detected by means of giving test patterns to the primary inputs and measuring the power supply current of the experimental circuit board, with the hope that the experimental results can guide the theory research task.Design for testability is an important method in IC testing. A test pattern generator based on CUT's feedback is realized. To minimize the test times, chip areas and storage space, the presented method tests IC only by adding some feedback lines.