Research On Test Generation Algorithm For Integrated Circuit And Design For Testability

In recent years, with the rapid development of electronic information industry, some novel and exquisite integrated circuit appear constantly, and it has been applied in military, civil, commercial industries widely.Integrated circuit test is not only a key step in integrated circuit function verification, but also an important basis for product batch production control. Therefore, the test of integrated circuit is becoming more and more important. However, with the improving of the integration, the degree of integration become higher, the chip size is getting smaller and smaller, per unit area power consumption and pin number increase a lot, integrated circuit test has become more and more difficult, the cost of test has become higher and higher. So we have to improve the integrated circuit test and find new testing method to deal with the fast developing integrated circuit.This paper first introduces the testing principle, method and technology used in integrated circuits, which covers a variety of test method on mixed signal integrated circuits, the test of digital and mixed circuit and circuit design for testability is probed. In order to decrease the testing cost and improve the fault coverage, the testing engineer have to reduce the test vector generation time and applying time, so as to shorten the test cycle. In the integrated circuit testing process, test vector generation is an important part, this paper focuses on the study of various test vector generation method. Design for testability can make the difficult and complex process be simple and easy, in a variety of design for testability, built-in self test is the fastest development, is also most extensive application, therefore, this paper do a lot of research on it.