Research On Key Technologies Of Time-sensitive Networking Chip Cyclic Forwarding Queue

With the continuous development of industrial control,onboard switching and other fields,traditional fieldbus technology has been unable to meet the demand for deterministic transmission on the network.Time-Sensitive Networking(TSN)is a key technology that can provide low-latency and low-jitter transmission services for the network by giving "time" characteristics to the standard Ethernet.In recent years,it has been widely favored by industry and academia.Cyclic Queuing and Forwarding(CQF)is a shaping mechanism used to provide deterministic transmission services in TSN.Because of its simple implementation and configuration,it has good application prospects in traffic planning.However,the CQF described in the standard lacks network edge time planning,which makes the CQF mechanism prone to traffic congestion during the deployment process,which in turn leads to the loss of critical messages.Traffic planning is the key to TSN chip applications.Its function is to map critical traffic to specific time slots on the network for transmission.Different planning results have different buffer requirements.FPGA-based TSN switch customization is an important way of TSN chip design,and minimizing TSN chip buffer resources is of great significance to reducing FPGA volume and power consumption.In order to enable the CQF mechanism and minimize the TSN chip buffer resources,this paper focuses on the research on the key technologies of CQF traffic planning.The main work and innovations include:(1)A CQF-oriented implementation architecture Mash CQF(Make Schedule for CQF)is proposed.Mash CQF is based on the TSN network centralized control model to realize the decoupling of the control plane and the data plane.The Mash CQF control plane is responsible for generating planning and configuration information for the entire network,and then delivering the configuration to the data plane.The Mash CQF data plane is responsible for guiding the deterministic transmission of critical traffic based on configuration information.(2)In-depth research on the key technologies of Mash CQF’s architecture.First of all,in order to ensure the buffer requirements of critical traffic,a TSN chip buffer management mechanism supporting for Mash CQF is proposed.Secondly,in view of the characteristics of the CQF mechanism,planning constraints based on Mash CQF is proposed;finally,based on the idea of random selection and multiple rounds of iteration,a traffic planning algorithm RSC(Random Schedule for CQF)is proposed to minimize the buffer resources of the TSN chip.(3)The Mash CQF prototype system was implemented,tested and evaluated based on the TSN open source chip "Fenglin No.1".Simulation results show that Mash CQF can reach the theoretical values of end-to-end delay and jitter defined by the CQF mechanism,At the same time,it benefits from both low time overhead and low buffer resource overhead.In summary,in order to solve the problem that CQF lacks abilities of network edge time planning,a CQF-oriented implementation architecture Mash CQF is proposed.Mash CQF is with the characteristics of high deterministic,low buffer resource overhead,and low time overhead,its research results have important reference value for CQF deployment in TSN chip applications.