FPGA System Implementation Of Data Acquisition And Control In Strong Interference Environment

With the continuous development of modern industrial technology,more and more nonlinear equipment is applied in industrial field.The harmonic interference brought by nonlinear equipment is accompanied by the severe electromagnetic interference caused by high current and high voltage,resulting in the interference environment faced by the system becomes more complex.Harmonic interference usually affects system operation in a coupling way,while electromagnetic interference directly affects electronic circuits in the form of electric and magnetic fields.Analog acquisition signals and communication signals transmitted in the form of voltage are more likely to be affected by interference,which may lead to analog signal acquisition anomalies or transmission error,resulting in system operation faults.Aiming at this difficulty,this paper establishes a relatively universal data acquisition and transmission system under strong interference environment through the combination of hardware and software.This system is based on the field programmable gate array(FPGA)of Microsemi IGLOO2 series with high reliability.It has the characteristics of deterministic behavior and simple structure,which is conducive to the supervision and forensics of the system.Therefore,it is suitable to be used as the control core of the system in the strong interference environment.Based on the actual project,this paper proposes the following improvements and innovations for the design of data acquisition and control system under strong interference environment,including:(1)This paper proposes a method to realize rapid self-healing when AD collection is abnormal without stopping the machine.The hardware is used to design a conditioning circuit to complete the conditioning of the acquisition signal,play the function of filtering and anti-interference of the acquisition channel,and realize the redundancy of the acquisition channel through the hardware.By programming a fair polling arbitrator and AD self-healing module,the AD self-healing module can detect the running status of the AD,and can send the reset enable to the AD chip with abnormal collection,so that it can quickly self-heal.The arbitrator can arbitrate the data collected by redundant channels,and move the channel out of the polling sequence when the channel collection is abnormal.To ensure the reliability of the collected data,the channel is added back to the polling sequence after it has completed self-healing.Finally,reliable acquisition data is transmitted.(2)An interleaved XOR codec method is proposed to realize the high reliability transmission of UART protocol.In this method,dual channel transmission structure is used in the hardware structure,namely the first channel and redundant channel.Each channel is composed of a group of UART transceivers.In the algorithm coding module,the interleaved XOR algorithm is used to re-encode the original data,and the re-encoded data is transmitted through redundant channels by using UART protocol.Sampling game is performed on the received data at the receiving end of dual channels to deal with burr signals caused by strong interference,and the data recovery module is designed by using the same interleaved XOR algorithm at the receiving end and the sending end.When the dual-channel receiving data is abnormal,the data recovery module is used to recover the abnormal data.This method has the function of error correction coding,and realizes error detection and error correction of transmitted data by increasing redundant information.(3)A fast self-detection method of isolation chip is improved.The programmable excitation signal is sent to the isolation chip by FPGA,and the signal is looped back to the FPGA after passing through the isolation chip,so as to quickly detect whether the isolation chip is working properly,and the delay parameter of the isolation chip can be accurately measured by using the two-stage system progressive algorithm.