Research On Ultra-Low Offset Integrated Operational Amplifie

In recent years,with the development of analog integrated circuits,new requirements and challenges have prompted the continuous improvement and development of operational amplifiers.The research and design of operational amplifiers with low power consumption and low offset has always been a hot spot in the development and research of analog circuits.In many measurement and control systems,integrated operational amplifiers are usually used to amplify and process weak electrical signals,and the operational amplifiers used are required to have ultra-low offset voltage and drift,low bias current and high common-mode rejection ratio.Looking forward to the future,ultra-low offset operational amplifiers will play an increasingly important role in different fields such as precision test instruments,medical equipment,and even national defense and military.The thesis first expounds the theoretical basis of the operational amplifier,and compares and analyzes the source of the offset and the method of reducing the offset between the BJT process and the CMOS process.The design method of the ultra-low offset operational amplifier is analyzed emphatically,and the key technologies used in the design process are considered,and how to reduce the bias current and offset voltage is considered from the circuit structure and layout design.At the same time,the index parameters and simulation methods of operational amplifiers are also introduced.Aiming at low offset voltage and low bias current,the paper adopts a three-stage amplification structure in circuit design to achieve high voltage gain.The bias circuit uses PTAT current source and a composite current source that has nothing to do with the first-order temperature as the circuit at all levels.Provide a suitable static operating point;the input stage uses a base current compensation circuit to reduce the input bias current and a diode trimming circuit to reduce the offset voltage;the gain stage uses a JFET differential pair tube to increase the gain,and uses nested Miller compensation to improve the circuit.Stability;in order to achieve high power output,it adopts a class B output stage with all N tubes.In this paper,the 40 V bipolar technology of a domestic company is used to design the circuit based on Cadence software,and the circuit simulation is completed using Specter software.The simulation results show that the maximum input offset voltage is 2.2μV;the input bias current is 0.7n A;the input imbalance current is 1.026 n A;the minimum open-loop voltage gain was 138.7d B;the common-mode rejection ratio was 154.5d B;the maximum single-channel current is 928μA;in the power supply voltage is 15 V and the temperature range is-55～125,the simulation results all meet the design requirements.Based on the Virtuoso tool,the drawing and verification of the dual-channel layout were completed,and the parasitic parameters were extracted for post-simulation verification.After the tape-out is completed,the wafer test is carried out,and the sampling chip has normal functions.After the trimming is completed,further packaging and testing are carried out.The test data shows that :in the full temperature range,the maximum offset voltage is-25.3μV;the offset voltage temperature drift is 0.025μV/℃;the input bias current is-3.535 n A;the input offset current is-0.825 n A;the power supply rejection ratio is 130.5d B;the common mode rejection ratio is146.9d B;the open-loop voltage gain is 134.2d B;the power supply current is 679μA,and all the indicators meet the expected requirements except the bias current.