Research On Interference Suppression Techniques For Multi-Carrier Non-Orthogonal Multiple Access(NOMA) Systems And Its FPGA Implementation

Power Domain non-orthogonal multiple access（PD-NOMA）is a technique that distinguishes users in the power domain using non-orthogonal power allocation.This technique not only effectively improves spectrum efficiency and system throughput but also enables fast network access or exit,with lower transmission waiting time,enhanced user fairness,and the ability to support more users.However,under jamming conditions,PD-NOMA can cause subcarriers within the jamming frequency band to be unavailable,and can severely affect the synchronization of periodic signal synchronization that relies on synchronization sequences,leading to receiver synchronization failure and communication system breakdown.Therefore,to ensure good performance of multi-carrier NOMA systems in jamming scenarios,the key issue to be addressed is interference detection and suppression.Thus,this thesis focuses on the simulation and implementation of anti-jamming PD-NOMA link systems.First,this thesis constructs a two-user PD-NOMA link,designs the synchronization segment and variable-length data segment in the frame structure of the transmitting end,and reviews two existing frequency-domain interference detection and suppression algorithms:Forward Continuous Mean Elimination（FCME）algorithm and Continuous Mean Exclusion（CME）algorithm.The performance and resource consumption of the two algorithms are analyzed,and the CME algorithm with lower resource consumption is selected for hardware implementation.In addition,the synchronization algorithm,channel estimation,and serial interference cancellation algorithm in the receiver under jamming conditions are also designed.Next,This thesis conducts hardware implementation of anti-jamming PD-NOMA link for two users and analyzes the hardware resource consumption of the CME algorithm and link.The conclusion is that the resource consumption of the CME algorithm and PD-NOMA link for two users is normal,mainly due to the consumption of lookup tables and on-chip registers used for large amounts of data caching and comparison operations,as well as the implementation of various logical structures and the use of IP cores such as addition and subtraction,with the divisor consuming more on-chip registers.Then,this thesis conducts on-board testing of the anti-jamming PD-NOMA link for two users,generates jamming using a signal source,and verifies the functionality of the CME algorithm and multi-carrier NOMA link on the board.Compared with simulation,the hardware implementation of the CME algorithm has a missed detection probability of less than 10^-5,indicating good interference detection performance and meeting design requirements.The link test results are consistent with the simulation,with user 1 and user2 performance degradation of about 2 d B under no jamming or jamming conditions,which ba SICally satisfies the design requirements.Finally,this thesis summarizes the research status of anti-jamming PD-NOMA links for two users,points out the shortcomings of this thesis,and proposes future research directions for further investigation.