Research On Sub-Pixel Level Wafer Overlay Error Measurement Algorithm

Chips are the core and cornerstone of high-tech manufacturing,which determines the development of high-tech industries.Photolithography is an extremely critical part of the chip manufacturing process.It can be said that the quality of photolithography directly determines the performance of the chip.A chip is made up of multiple layers of circuits,and the manufacture of a chip usually requires dozens of photolithography operations to complete.The alignment deviation between adjacent circuit layers in the chip is also called overlay error.The rapid measurement and accurate evaluation of overlay error is the key to the optimization of lithography machine operating parameters and process yield management.However,at present,China is still in a relatively blank stage in the field of overlay error measurement equipment,and related equipment is mainly imported from abroad.However,incidents such as "stuck necks" and technology blockades that have occurred frequently in recent years have shown Chinese people that it is a great potential risk that core technology is controlled by others.In the context of globalization and intensified competition,if a country does not have independent innovation ability,it will be difficult to occupy a dominant position in international competition.The in-depth research on the overlay error measurement algorithm is conducive to breaking through the core technology of overlay error measurement equipment,and realizing the independent research and development and production of overlay error measurement equipment as soon as possible.This article originates from a research and development pre-research project of an overlay engraving machine in cooperation with a semiconductor high-tech enterprise.It is benchmarked against the mainstream Archer 100 overlay error measurement equipment in the current market(its algorithm is not disclosed).The project aims to overcome the core technology of overlay measurement and carry out technical breakthroughs.With the continuous development of the integrated circuit manufacturing process,the size of transistors on the chip is getting smaller and smaller.In order to realize these tiny structures,the minimum line width in the manufacturing process is continuously shrinking,and the requirements for overlay error accuracy are also increasing.This paper takes Image-Based Overlay error measurement technology as the main research content,and proposes a sub-pixel-level overlay error measurement algorithm that combines rough edge location and precise edge location.The accuracy of the algorithm is below 5 nanometers,meeting the accuracy requirements of the Archer 100 overlay error measurement system using the same image data,and the pre-research project has achieved phased sucess.The algorithm proposed in this paper includes two processes of pixel-level coarse positioning and sub-pixel level precise positioning.The sub-pixel level precise positioning is based on the results of pixel-level rough positioning.The main contributions and innovations of this paper are summarized as follows:(1)A pixel-level overlay mark edge localization algorithm based on template matching is proposed,which realizes accurate positioning of the pixel-level overlay mark edge.Since the subsequent sub-pixel-level precise positioning will be based on the result of the pixel-level coarse positioning,the accuracy of the result of the pixel-level coarse positioning is very important.In pixel-level coarse positioning,in order to eliminate the interference of edges that do not belong to the overlay mark and improve the accuracy of pixel-level edge positioning,this algorithm is proposed.Use this algorithm to locate the edges in the X and Y directions of 40 images,and the error is no more than 1 pixel.Among them,there are 36 images in the X direction with an error of no more than 0.5 pixels,and 35 images in the Y direction with an error no more than 0.5 pixels.(2)A sub-pixel level overlay mark edge positioning algorithm based on the Sigmoid model is proposed,which realizes the precise positioning of the sub-pixel level overlay mark edge and the precise calculation of the overlay error.In the sub-pixel level precise positioning,based on the edge shape features in the overlay mark image,and on the basis of comparative analysis of 6 edge detection models,the Sigmoid edge detection model is selected for sub-pixel level precise positioning of the edge,and the positioning accuracy reaches 0.06 pixel.In addition,the feasibility of applying machine learning to the field of overlay error measurement is explored.This paper selects the FSRCNN neural network model to reconstruct the overlay marked image,and uses image segmentation,transfer learning and other technologies to alleviate the cold start problem caused by the scarcity of data sets and random initialization of model parameters.Then,the overlay error is calculated using the reconstructed image,and the feasibility of applying machine learning to the field of overlay error measurement is discussed.(3)Hardware implementation and optimization of the overlay error measurement algorithm proposed in this paper.Use the vivado HLS simulation and performance analysis tool to carry out hardware simulation and performance analysis of the overlay error measurement algorithm proposed in this paper.Through the optimization of scheduling between functions,optimization of loop code and optimization of array resources,without losing the accuracy of the algorithm,use common FPGA chips(Xilinx xc7z020clg400-2 series chips)increase the running speed of the algorithm by more than 10 times(compared to Intel i5 9300 CPU),and effectively reduce the resource usage.