| With the development of VLSI technology,the scale and structure of VLSI are becoming larger and more complex.Therefore,VLSI arrays are widely used in industrial systems.However,with the increasing density of VLSI arrays,some processor elements(PE)often fail due to overload or overheating during massively parallel computing operations.It will takes a lot of manpower and material resources to directly replace the VLSI array which containing faulty components,and this is also the waste of integrated circuit resources.Therefore,on the premise of ensuring the effectiveness and real-time of VLSI array,it is necessary to take effective fault-tolerant technology to build a fault-free target array to ensure the reliability of integrated circuits.The existing fault-tolerant technologies include redundancy approach and degradation approach.Because the redundancy approach will consume a lot of resources,and degradation approach achieves fault tolerance by reconstructing the interconnections between elements,which get high flexibility,so the research in this paper is based on the degradation approach and mainly focuses on the fault-tolerant technology of 3D VLSI arrays,and the research objectives includes improving the scale of the reconstructed target array and reducing the interconnection length of the reconstructed target array.Addressing the scale growth issue of target arrays.Based on the existing algorithms,an improved method is proposed.By finding the bottleneck which limits the growth of the target array size,while removing the bottleneck in the reconstruction process,a compensation strategy is proposed to use some fault-free PEs on the bottleneck to replace the adjacent fault PEs,so as to improve the utilization of fault-free PEs in the reconstruction process and increase the size of the target array.Compared the running results with the existing algorithm,the feasibility of the proposed algorithm is verified.Experimental results show that the proposed algorithm can effectively increase the size of the reconstructed target array.Regarding the interconnection length issue of the reconstructed target array.Because the reconfiguration mechanism will reconfigure the connect mode between PEs,resulting in an increase in the interconnect length of the PEs in the target array,which caused the time delay and power consumption in the use of the array can’t be ignored.Therefore,this paper proposes an algorithm to reduce the interconnection length in the target array.This algorithm searches for a PE which get minimize the local interconnection length,and then expand around with the local optimization from this PE until a target array with optimized interconnection length is formed.Compared with the existing algorithm experimental results,it is verified that the proposed algorithm can effectively reduce the interconnection length in the target array.In addition,when evaluating the effectiveness of the interconnection length reduction algorithm,there is a key data called the lower bound of the interconnection length.This paper proposes a method to calculate the lower bound of the interconnection length of the target array.This method breaks the locality of the existing methods and calculates the lower bound of the interconnection length through the global aspect.The experimental results show that this method can calculate the lower bound of interconnection length more accurately than the existing methods,providing a strong guarantee for the accurate evaluation of the effectiveness of the algorithm to reduce interconnection length. |
