| The integration of satellites and 5G can fully leverage the advantages of satellite communication and ground communication,achieving seamless coverage and addressing ground communication interruptions caused by natural disasters and other factors.However,satellite communication systems are susceptible to malicious high-power interference.Under the influence of interference,the performance of the communication system can significantly degrade,reducing the reliability of signal transmission.In addition,the relative motion between satellites and high-speed user terminals introduces significant Doppler frequency offset and Doppler frequency offset variations.Therefore,this thesis focuses on the characteristics of satellite communication systems and further investigates anti-jamming methods and time-frequency synchronization algorithms based on 5G NR(5 G New Radio).The main contents of this thesis are listed as below:(1)This thesis introduces the physical layer frame structure of 5G NR,OFDM(Orthogonal Frequency Division Multiplexing)system,types of interference and anti-jamming methods.It focuses on analyzing the impact of severe interference and high dynamic environments on the demodulation performance and time-frequency synchronization performance of communication systems.The research indicates that in satellite communication scenarios,the frame structure of 5G and traditional time-frequency synchronization algorithms are not able to withstand significant interference.Therefore,this thesis proposes to incorporate spread spectrum technology into the design of 5G physical layer transmission waveforms,and countering interference by adjusting the spread spectrum factor.(2)This thesis analyzes the maximum Doppler frequency offset and the maximum rate of Doppler frequency offset variations between low orbit satellites and high-speed user terminals.However,OFDM technology is sensitive to frequency offset and its rate of change,and coupled with the impact of interference,it is necessary to further enhance the anti-jamming and anti-frequency offset capabilities of time-frequency synchronization algorithms.This thesis primarily focuses on improving the performance of time-frequency synchronization in two aspects:1)In terms of SSB(Synchronization Signal and PBCH Block)design,this thesis increases the number of subcarriers in the frequency domain to 600,while keeping the time domain unchanged.The lengths of PSS(Primary Synchronization Signal)and SSS(Secondary Synchronization Signal)sequences are extended to 511;2)Regarding the time frequency synchronization algorithm itself,a SSS assisted PSS multi-step joint anti-jamming timefrequency synchronization algorithm is proposed.Specifically,the approach involves initially employing a two-dimensional time synchronization algorithm by SSS assisted PSS,aiming to identify a coarse time synchronization point.Subsequently,based on the coarse time synchronization point,integer and fractional frequency offset estimation and compensation are performed.The fractional frequency offset estimation includes two components:PSS sweep coarse frequency offset estimation and SSS assisted PSS cross-correlation for fine frequency offset estimation.After compensating for all frequency offset,precise time synchronization and frequency offset compensation is performed once again to eliminate the impact of frequency offset on time synchronization.The proposed approach demonstrates good error performance in scenarios characterized by high interference and low signal-to-noise ratio.(3)This thesis designs a physical layer downlink level platform using simulation software to verify the proposed waveform transmission scheme and SSS assisted PSS multi-step joint anti-jamming time-frequency synchronization algorithm.Simulation analysis indicates that the proposed scheme and algorithm in this paper can withstand interference with a JSR(Jammer-to-Signal Ratio)of 12dB.Additionally,this thesis utilized the Verilog language on the FPGA hardware development platform Vivado to design and implement the physical layer ’s transmission and reception processes,as well as the proposed algorithm.It provides detailed explanations of the logic design principles and implementation processes for each module.Through Simulator simulations,the thesis presents the simulation results of each module,verifying the rationality of the platform’s logic,functional design,and timing. |
