Deterministic Low-Latency Scheduling Strategy For Optical Interconnects In Data Centers And FPGA Implementation

With the rapid development of time-sensitive network technologies,networks,including data center networks,are placing higher demands on the latency of traffic scheduling.Packet shaping as a data processing method for traffic at the node can ensure the consistency of packets.Based on this,combined with the deterministic scheduling algorithm in TSN networks,a deterministic low latency data center network topology can be realized.In the data center network topology,the End-host nodes,as the access side of data traffic,need to handle a.large number of traffic of different services.The packet size of these flows varies,leading to the complexity of deterministic scheduling algorithms.Packet shaping,as a traffic processing technology,removes the problem of different packet sizes for different services by processing traffic into uniform packets with customized packet formats.It effectively improves the simplicity of deterministic scheduling algorithm.Based on the practical requirements of the above background,this thesis designs a traffic scheduling strategy based on custom Cell frames,and validates the relevant modules of the scheduling strategy by FPGA after a clever module design for the data center End-host node.The main work of this thesis is as follows.(1)In this thesis,a traffic scheduling strategy based on custom Cell frames is proposed for the problem of inconsistent traffic packet sizes at the data center network End-host nodes,which designs a fixed-size custom Cell frame.At the data center network End-host nodes,the data traffic of different services is shaped into fixed-size Cell frames and then received by scheduling and reduced to the data traffic before processing.This strategy provides the feasibility for deterministic timing scheduling algorithm.(2)In this paper,the deterministic traffic scheduling strategy based on custom Cell frames is combined with the advantages of FPGA to functionally validate the relevant modules in the data center end node.The corresponding functional modules in the scheme are tested and verified on the board by Verilog HDL language to ensure that the function of each module and the total scheme module is normal and the timing is normal.The experimental results show that the scheduling strategy based on custom Cell frames achieves full throughput in low-rate scenarios.