Chiplet Inter-Chip Parallel Interface

With the increasing demand for chip performance from applications such as artificial intelligence and big data,in the post-Moore era,due to the slowing increase in transistor density and the limited area of single-chip manufacturing,the improvement of single-chip computing power has encountered a bottleneck.Therefore,some scholars put forward the Chiplet design method based on the idea of "breaking the whole into parts",which provides an important idea for continuing to improve the computing power density.However,the Chiplet design method requires a high-speed transmission interface between Chiplets,to meet the high-bandwidth data transmission requirement between chips.The current Chiplet inter-chip interface design mainly needs to solve two problems:(1)the contradiction between high-bandwidth inter-chip transmission requirement and high-density interconnection cost;(2)system reliability problem is caused by immature high-density interconnection technology.In view of the above problems,this paper designs and implements a new high-speed parallel interface between Chiplets,which introduces an arbitration mechanism and a fault-tolerant calibration circuit.The interface is designed to improve the utilization rate of signal lines between chips and system reliability.The research work of this paper mainly includes the following three parts:(1)A channel sharing circuit based on time division multiplexing and arbitration mechanism is designed.In view of the problem that the limited inter-chip signal lines can not meet the high-bandwidth transmission requirement on-chip,this paper introduces a time-division multiplexing mechanism and an arbitration mechanism.Among them,the time-division multiplexing mechanism uses multiple on-chip nodes to time division multiplex the inter-chip interface.The method reduces the inter-chip signal lines to 1/8 of the original,and cooperates with the arbitration mechanism to further improve the utilization rate of the inter-chip signal lines.Finally,the utilization rate of inter-chip signal lines is increased by83%.The channel sharing circuit realized by this method can not only improve the parallelism of interface data transmission,but also effectively reduce the cost of high-density interconnection.(2)A JTAG-based test circuit and fault-tolerant calibration circuit are designed.Firstly,in view of the problem of poor bump contact during the assembly of the inter-chip interface,this paper designs a JTAG test circuit and fault-tolerant circuit,in which the JTAG test circuit can check the connectivity of inter-chip signal lines.The fault-tolerant circuit ensures that when the signal lines between chips are not connected due to process reasons,the system can still work normally through the redundant signal lines.Secondly,for the clock waveform distortion problem in the inter-chip interface,a calibration circuit is designed in this paper,which ensures the data reliability under high-frequency transmission by calibrating the high-speed clocks of the receiver and transmitter respectively.The combination of the two improves the reliability of the system.The experimental results show that if there is an unconnected inter-chip signal line in the output even chain or the output odd chain,the system can still work normally through the redundant shift operation.(3)The Chiplet inter-chip parallel interface hardware structure is designed and implemented,including the MAC layer module,the physical layer module and the test module.Finally,the internal modules are designed and implemented.The MAC layer module is responsible for encapsulating and analyzing the on-chip signals,the physical layer module is responsible for sending and receiving signals through the inter-chip signal lines,and the test module is responsible for testing the connectivity of the inter-chip signal lines.The experimental results show that the data transmission rate of the Chiplet interface designed in this paper is as high as 30GB/s,which can meet the data transmission requirement between Chiplets,and has the advantages of strong reliability and high transmission speed.The Chiplet inter-chip interface design meets the predetermined requirements of the project.