| Performance optimization of parallel programs on many-cores is a hot topic.In parallel programs,multiple threads often need to communicate frequently.The efficiency of inter-core communication is an important factor that affects the performance of a parallel program.The efficiency of inter-core communication based is significantly affected by the cache system and cache coherency protocol of many-core processors.To evaluate and optimize the performance of inter-core communication,it is necessary to understand the architecture and working mechanism of the cache system.There have been a lot of work to evaluate the cache system on traditional x86 many-core processors,but there is little research on ARMv8 many-core.In addition,as one of the basic operations of intercore communication based shared memory,the performance of barrier synchronization on ARMv8 many-cores is also not satisfactory.This paper study the cache system of ARMv8many-cores firstly.Then we evaluate seven mainstream barrier synchronization implementations on ARMv8 many-cores.Finally,we propose a targeted optimization method for barrier synchronization.The main research contents of this paper are as follows:(1)We develop a benchmark suite(wr Bench)for the ARMv8 many-cores to measure the performance of its cache system.The benchmark transfer data between different cores through pthreads multithread programming,and adopt an effective mechanism to control the initial position and coherency state of data.We use wr Bench on three different ARMv8 platforms(Phytium 2000+,Thunder X2 and Kunpeng920)to obtain quantified performance data including latency and bandwidth while demonstrating the potential of wr Bench.Through the analysis of these quantified performance data,the working mechanism of each processor cache system is revealed.(2)We study and implement seven classical barrier synchronization algorithms on three ARMv8 platforms,and measure their actual overhead with EPCC micro-benchmarks.We abstract the inter-core communication involved in barrier synchronization to the basic operation of loading and storing shared data in cache,and model the overhead of these cache operation.By analyzing the cache behavior patterns of different barrier synchronization algorithms and modeling the cache operation overhead,we analyze the bottleneck problems of these algorithms on ARMv8 platform.(3)Based on the static f-way tournament algorithm,we optimize the barrier synchronization for ARMv8 many-cores.By extending the granularity of arrival flags,we try to avoid interference between threads in Arrival-Phase and reduce the possibility of inter-core communication across core clusters.In addition,we develop a NUMA-aware algorithm for ARMv8 many-cores by modifying the notification tree structure.The results show that our optimization yield 12.6x performance improvement over the GCC implementation and 4.7x improvement over the LLVM implementation,translating to 1.6x improvement over the state-of-the-art best-performing algorithm. |
