Research And Implementation Of A Micro Kernel Real-time Analysis Tool Based On ARM Architecture

In order to ensure real-time tasks can be completed before the deadline,real-time systems need to be analyzed to avoid catastrophic consequences.Worst-Case Execution Time(WCET)of a real-time task is an important indicator for evaluating the real-time performance of an operating system,which was real-time operating system input criteria for real-time task analysis.Static WCET analysis method has become the main WCET analysis method because of it’s safety and reliability.Among them,because of the dynamics and uncertainty execution results of processor micro-architecture,like cache,branch predictor,and pipeline,modeling the effects of micro-architectural features become a research difficulty of static WCET analysis.However,in the current research,the analysis of each module of the processor micro-architecture is independent,the mutual influence between different modules is rarely considered.Based on this background,This thesis make research on the principle and key technologies of the open source WCET analysis tool Chronos.Based on the research results of previous scholar,this thesis focuses on the following research:1.For the cache impact on program execution time,this thesis uses Cache Confiltc Graph(CCG)to analyze the impact of cache line conflicts and then combined with analysis of cache conflict graph and control flow generate linear constraints for the WCET objective equation.2.For the predictor,the method based on the history pattern of branch instructions is used to analyze the influence of branch predictor on program execution time,and the control flow graph is extended by combining the jump result of branch instructions.Finally,the linear constraints of WCET objective function based on history state is established.3.In terms of the interaction between the cache and the branch predictor,this thesis assumes that the instruction cache pre-fetching strategy is wrong-path pre-fetching, and then represents miss branch prediction by adding virtual nodes in the cache conflict graph to analyse the interaction between cache and predictor.Finally,this thesis integrates the Simple Scalar/ARM simulator in the analysis tool,and uses the analysis tool to conduct experiments on some test cases in the Maradalen University WCET Benchmark.The experimental results show that the analysis tool designed in this thesis can analyze the safe WCET value under the consideration of the interaction between the modules of the micro-architecture,but for some complex test cases,the tool cannot works.So the next plan will continue focus on modeling the impact of processor macro-architecture.