Communication And Clock Synchronization Design Of Data Acquisition Module Based On Fibre Channel Protocol

With the further development of distributed network,there is a growing demand for data link communication with high bandwidth,low latency and low bit error rate in engineering applications.In this case,Fibre Channel protocol has a wider application scenario,so it has important research value。In the context of high-speed communication with high bandwidth,the clock synchronization accuracy requirements of communication networks are also continuously improved.The traditional NTP clock synchronization method has limited accuracy.The IEEE 1588 clock synchronization protocol based on PTP has great development potentialIn this thesis,a 12.5Gbps serial rate data acquisition module based on Fibre Channel protocol is designed,and the clock synchronization accuracy is better than 1ns.A total of two boards are designed,and technologies such as FC protocol communication,IEEE1588 clock synchronization protocol are studied.The main work of this project is as follows:(1)The overall implementation scheme of hardware circuit.First of all,according to the communication function requirements of the host computer and the instrument end of this project,the overall hardware scheme is designed to realize the transfer of PCIe-FC-local bus by the master adapter card and the slave adapter card.Secondly,according to the overall hardware design scheme,the hardware circuit scheme of photoelectric conversion module,clock system and PCIe interface is formulated,and the specific hardware design is given.(2)The communication module FPGA implementation.First of all,by analyzing the two implementation schemes of PCIe interface,XDMA ip hard core based on Xilinx FPGA is selected.After the handshake timing analysis of the AXI bus interface of the ip core,the user interface logic of PCIe data receiving is designed,and the PCIe interface communication is realized;Secondly,according to the FC protocol standard,take the FC protocol link requirements and the FC data frame format as a reference,the FC protocol port state machine,the FC protocol sending module and the FC protocol parsing module are designed to realize the basic FC protocol communication;Finally,in order to realize the data communication between the slave adapter card and the instrument terminal board card,considering the complexity of the digital logic design and the limitations of the actual circuit,the local bus design scheme of parallel bus is adopted.(3)The clock synchronization module FPGA implementation.First of all,the various implementation schemes of time synchronization and frequency synchronization are compared,and the time synchronization scheme of local clock counter+IEEE 1588 synchronization protocol and the frequency synchronization scheme of constant temperature crystal oscillator+DDMTD phase measurement are selected;Then,transmit the IEEE 1588 clock message packet between the two boards,test the link delay and time deviation,and realize time synchronization;Finally,measure the random phase of the remote thermostatic crystal oscillator clock and the recovery clock of the GTH high-speed serial transceiver on the slave adapter card,the phase difference between the recovery clock and the local thermostatic crystal oscillator clock,and then adjust the phase of the local clock through the digital hybrid PLL of the FPGA to realize the phase synchronization of the local crystal oscillator clock and the remote crystal oscillator clock,and coordinate with the high stability of the thermostatic crystal oscillator output to achieve frequency synchronization.The experimental results show that the data acquisition module designed in this project achieves the 12.5Gbps serial communication rate and clock synchronization accuracy better than 1ns required by the index.