Design Of Data Plane In SDN Network Packet Processors Based On FPGA

It’s difficult to adapt to the trend of network development and innovation due to the coupling of software and hardware and the closed control interface in traditional network middleware.Software Defined Network(SDN)makes the network more flexible and intelligent by separating functionality of control and forwarding,which adapts to this trend and has great research significance and application value.The SDN data plane completes the processing and forwarding of network packets according to the rules set by the controller,which is the key to determining network performance.With the development of the Space-air-ground integrated information network and communication technology,the emergence of various new network protocols,the increasingly rich network services and the increasing network bandwidth all put more stringent requirements on the implementation of the SDN data plane.This paper conducts in-depth research on the design and implementation methods of SDN data planes for addressing high-performance network packet processing and forwarding needs.The main contents are:(1)To design the network packet processing flow and functional module structure,and propose the data plane implementation architecture for the requirements of high-speed processing and forwarding,custom protocol processing and quality of service assurance in data plane.(2)A fast matching algorithm based on flow table chunking is proposed to address the problem of slow matching speed resulting in reduced processing and forwarding rate when the flow table size keeps increasing,which has the advantages of fast matching speed,low resource consumption and low implementation complexity.(3)To address the problems that the traditional priority queue scheduling mechanism is inefficient and cannot guarantee fair priority queue output bandwidth allocation and maximum forwarding delay requirements at the same time,a high-performance priority queue scheduling mechanism is proposed,including VIQ-based virtual priority cache structure,EDF-based priorities parallel in-queue scheduling algorithm and Improved-DRR out-queue scheduling algorithm.This mechanism avoids the queue head blocking problem and provides fine-grained priority queue output bandwidth allocation and latency guarantee functions.Experimental tests show that the SDN network packet processor data plane designed in this paper achieves the processing and forwarding functions of both traditional Ethernet protocols and a custom protocol,which can guarantee the fairness of output bandwidth allocation and maximum delay requirements during 8-level priorities queue scheduling at the same time;it supports single-level flow table depth of 2000,single-port processing and forwarding rate of about 5.19 Gbps,and maximum forwarding delay of about 1.228ms;it has the advantages of fast processing and forwarding rate,support for dedicated protocol processing and finegrained quality of service assurance functions.