Research And Implementation Of Low Power Graph Convolution Neural Network Accelerator Based On FPGA

With the development of AI,graph convolution neural network(GCN)has come into people’s vision and has been more and more widely used in social networks,electronic circuits,traffic prediction and other fields.This paper focuses on the placement problem in the chip design process,and proposes an improvement on the traditional placement algorithm by using GCN and reinforcement learning;On the other hand,in order to promote the implementation of GCN in the Internet of things,embedded mobile terminal and other scenarios,it is necessary to develop a low-power,small area and flexible GCN hardware platform.Comparing the advantages and disadvantages of various hardware platforms,this paper selects FPGA platform to realize the special accelerator of the above GCN.The main work of this paper is as follows:(1)The research status of FPGA neural network accelerator is analyzed,the popular placement algorithms are compared,and the application of reinforcement learning method in placement problem is studied.(2)Based on the analysis of layout problem and simulated annealing algorithm,an improved reinforcement learning simulated annealing algorithm based on graph convolution neural network is proposed.Aiming at the disadvantage of slow random exploration of simulated annealing algorithm,the reward prediction network based on graph convolution is optimized,and the algorithm is implemented on VTR open source design software.Experiment results show that the improved algorithm can find a better placement earlier than the random method.(3)A reward prediction neural network accelerator based on FPGA is designed.This paper analyzes the computational characteristics of graph convolution neural network.Focusing on reducing resources,reducing power consumption and improving speed,sparse matrix multiplication and pipeline are used to accelerate the neural network.(4)The accelerator of reward prediction network is realized on PYNQ.This paper completes the hardware implementation of the network on the pynq development board based on vivado HLS.Experiments show that the accelerator uses most of the hardware resources.On the premise of ensuring a certain processing speed,the power consumption is far less than that of CPU and GPU.