Design And Implementation Of SOC-based Arrhythmia Classification System

Arrhythmias are very common in clinical practice and can result in a waveform with an abnormal pattern and rhythm in the central beat of the ECG signal.The timely and correct detection and detection of arrhythmias is of great importance in the early stages of clinical diagnosis and can prevent cardiovascular disease.In recent years,the classification of arrhythmias has become a hot topic of research in the field of physiological signal analysis.The electrocardiogram(ECG)is an important clinical diagnostic tool that can help doctors to detect and diagnose arrhythmias early.However,manual diagnosis of ECG is limited in real time,which may lead to patients missing the best time for treatment.To address these problems,arrhythmia classification algorithms can be implemented on edge-side smart terminals such as wearable devices,which enables real-time analysis and processing of ECG signals while improving the flexibility and safety of the device.This paper first introduces the background knowledge of arrhythmias and related algorithms,and discusses the feasibility and advantages of implementing arrhythmia classification algorithms on Zynq SOCs.By exploiting the excellent classification capabilities of convolutional neural networks in many fields,applying them to arrhythmia classification can effectively extract features of ECG signals and improve the classification accuracy.The main work of this paper is summarised as follows:(1)A four-layer wavelet thresholding denoising algorithm with db3 wavelet basis is applied to effectively remove noise,while a differential thresholding method is used to detect R-wave and perform heart beat segmentation according to R-wave position.In addition,experiments on five classification of cardiac arrhythmias were performed based on the MIT-BIH dataset using a designed convolutional neural network.The classification accuracy of the classification method was shown to be as high as 99.17% by the experimental results.(2)The HLS advanced synthesis tool is used to construct the wavelet threshold denoising IP and R-wave detection IP,while adding suitable optimization instructions to reduce the computational delay of the design;the Verilog HDL hardware description language is used to design the convolutional neural network IP,and the design is explored through parallel structure,resource reuse,pipeline processing,data fixed-point quantization and other optimization measures to optimize the acceleration.(3)Based on the five classification algorithms for arrhythmias based on the MIT-BIH dataset,this paper takes a hardware implementation of the hardware and software co-design approach on the Xilinx Zynq SOC hardware platform to complete an arrhythmia classification system with good classification effect,fast processing speed and low power consumption.In order to verify the effectiveness of the system,a series of experiments are conducted in this paper.The results show that the system achieves an average classification accuracy of 99.01%and an average time of 28.16 ms for individual heartbeat classification,achieving a speed-up performance of more than 7.34 times compared to a single ARM core on the pure PS side.