Fully-integrated Digitally Controlled Buck Converter Design Based On LADRC Algorithm

With the development of new energy technology,a large amount of clean electricity will be available to people,but the power supply voltage required for different process chips is different,so power management chips are needed to complete the conversion of power.Among them,according to the different control methods can be divided into digital control power supply and analog control power supply.The digital control power supply has the advantages of high portability,good antiinterference and flexible control compared with the analog power supply,which has become a research hotspot for universities and enterprises.In this dissertation,a fully integrated digital Buck-type converter is designed using LADRC as a digital controller.The overall design is implemented based on a VIS0.18μm CMOS process,and the layout and drawing of the digital and analog layout are completed.The detailed work is as follows:1.The feasibility of LADRC applied to Buck converter dual-loop control was verified by Simulink modeling,then the LADRC was discretized and implemented in Verilog,while the controller parameters obtained by the bandwidth method were further simplified by using the parameter scaling method,resulting in a 51.2% reduction in overall power consumption and a 52% reduction in layout area of the LADRC while ensuring the same output effect.The overall power consumption of LADRC is reduced by 51.2% and the layout area is reduced by 52%,which effectively reduces the design cost.2.A 1.5bit/ stage RSD Cyclic ADC with input voltage range from-5V to 5V and resolution of 12 bit was designed according to the requirement of voltage ripple 15 m V for Buck converter.The ADC adopts a fully differential architecture,which can effectively suppress the common mode disturbance.RSD coding is used to reduce the offset voltage of comparator to some extent.The simulation results show that the SNR of the ADC is 66.3524 d B and the ENOB is 10.484 bit,which meets the design requirements of the minimum 9.39 bits to recognize the voltage ripple of Buck converter.3.A 12 bit counting DPWM circuit is designed,which can generate two pulse signals PWM1 and PWM2 with 20 ns dead time and one signal Sampling.The signal corresponds to the midpoint of the inductance current waveform when it is high,and also serves as the enable signal of the sampling and holding circuit and ADC.AMS digital-analog hybrid simulation was conducted on the whole Buck converter,and the data showed that the power-on start-up stage required about 300μs,and the target value could be reached without overshoot,and the output voltage was stable at2.016 V.When the load changes from 2A to 1A,the recovery time is 337μs,and when the input voltage changes from 6V and 4V to 5V,the recovery time is 121μs and 123μs,indicating that the digital active disturbance rejection controller has a high transient response ability.