Design And Verification Of AXI Bus Based On Functional Safety Mechanism

Under the dual role of national strategy and market factors,the automobile production and sales volume in our country have been steadily ranked the first in the world in recent years.As the control core of automobile electronic system,the demand scale of automotive chip is increasing year by year.Because of the special application scenarios,the safety requirements of automotive chips are higher than those of industrial chips and consumer chips.Function Safety(Fu Sa),as a key technology to enhance safety,has become the focus of research on automotive chips.This paper follows the digital IC front-end design process,takes Fu Sa technology and Advanced e Xtensible Interface(AXI)bus for vehicle level radar chips as the research object,and studies the international standard ISO 26262 for Functional Safety of Road Vehicles and the AXI bus protocol.The design of AXI bus with functional safety mechanism is completed.By studying Universal Verification Methodology(UVM),the design of bus verification platform and the development of automated tools are completed.Finally,based on UVM verification platform,functional verification and fault simulation are completed,which fully verifies the completeness of the design.The main work in each development stage of the paper is as follows:In the design phase,this paper plans the architecture scheme of Network Interconnect Component(NIC)Intellectual Property core(IP)based on AXI bus protocol,and designs a set of comprehensive functional safety mechanism.This functional safety mechanism includes Error Correction Code(ECC)algorithm protection mechanism,hardware redundancy mechanism,and timeout monitoring mechanism.It can be integrated into the original AXI bus IP architecture to detect faults without affecting the inherent functions of the AXI bus.ECC algorithm protection mechanism is based on Hsiao coding technology,which can correct 1-bit data errors and detect 2-bit data errors when data errors occur in the key signals of each transmission channel of the AXI bus interface.Hardware redundancy mechanism based on dual-core lockstep technology,which can detect bus path data failure.Timeout monitoring mechanism adopts multi-channel design,which can simultaneously monitor the AXI bus read/write transaction association signal and read/write address channel handshake signal.If there is a signal timeout fault or abnormal timing fault,the timeout monitoring mechanism will alarm.In the verification preparation stage,based on the function points of AXI bus,this paper firstly designs and implements the AXI bus verification platform which can support two kinds of requirements: functional verification and fault simulation,including block-level bus verification platform and system-level bus verification platform.Then,in order to improve the verification efficiency,this paper uses System Verilog language and Python language,based on AXI bus verification platform architecture,through the study of code automation generation technology,designed an automatic generator for bus UVM verification platform.The generator supports recognition of Bus configuration information based on the Advanced Microcontroller Bus Architecture(AMBA)and can generate code files for the block-level or system-level AMBA bus UVM verification platform with one click.The verification platform has the functions of random drive signals generation,automatic data comparison and error reporting.In the verification stage,firstly,this paper uses the automatically generated AXI bus block-level verification platform to conduct block-level function verification for AXI bus bridge with multiple functional safety mechanisms.The pass rate of all test cases reached 100%,the functional coverage reached 100%,and the code coverage reached 100%.Subsequently,the fault simulation tool XFS of Cadence was used to carry out fault injection for AXI bus bridge.The diagnosis coverage rate of each failure model was higher than 95%,which means that the fault detection rate of the functional safety mechanism meets the ASIL-B requirements specified in ISO 26262 standard.Finally,based on the automatically generated system-level verification platform,this paper carries out system-level data path verification on the bus interconnection matrix of the chip,and the test case passes.The results show that the functional safety mechanism can effectively improve the safety of AXI bus,and the automatic generator of bus UVM verification platform can accurately complete the task of code generation,both of which meet the design expectations.