Design And Verification Of Key IP Cores For A Dedicate SoC With Pmsm Control Based On AMBA Bus

PMSM(Permanent Magnet Synchronous Motor)has been widely used in the field of motor control in recent years.PMSM is currently widely used in industrial robot,new energy automobiles,exoskeleton systems,missile rudders,unmanned aerial vehicles and other fields.However,in practice,traditional motor control chips such as MCU chips and DSP chips are becoming increasingly difficult to adapt to PMSM-based high-performance servo control systems due to their insufficient arithmetic power.Although FPGA chips can meet the arithmetic requirements,they are not versatile enough and the cost of the chips is too high when deployed in large quantities.Therefore,the design of a dedicated PMSM control chip for PMSM drive control has become an important breakthrough in the development of high-performance PMSM control systems.In this thesis,we design and integrate three key IPs on the basis of RISC-V general-purpose SoC to turn the general-purpose SoC into a PMSM-controlled dedicated SoC,and the main research of this thesis is as follows:(1)Design of key IPs.In order to achieve efficient hardware control of the PMSM,three key IPs are planned based on the RISC-V general-purpose SoC architecture: the coprocessor IP for accelerating single-axis and multi-axis PMSM vector control algorithms,the APWM IP for direct control of the PMSM,and the DMA IP for efficient on-chip data handling.This study also proposes and applies four special hardware design methods to reduce the hardware area and improve the control performance;for the APWM IP,this study configures multiple modes inside the IP to make it suitable for various motor control scenarios;for the DMA IP,based on the characteristics of vector control computing itself,this study therefore designs a multi-functional,low-area,low-cost IP with a high performance and low cost.For the DMA IP,a multi-functional,low-area-overhead DMA IP is designed with a dedicated handling mode for efficient handling of coprocessor results.The APWM IP and DMA IP in this study can be used not only in conjunction with the coprocessor IP for PMSM vector control,but also individually for other scenarios,as they are designed with the IP’s versatility in mind.This study has completed the development of three IPs based on the Verilog HDL hardware design language.(2)Module level functional verification and performance analysis of key IP.To ensure that the IPs are functionally correct,module-level verification was carried out by dividing the functional points of each IP,and the module-level verification results show that the IPs function as expected.In order to analyse the performance of the IPs,the Design Compiler tool and the Formality tool were used to synthesise and formally validate each of the three IPs.The synthesis report shows that the key IP can reach the target frequency of 72 MHz after synthesis,which meets the design requirements.The formal verification report shows that the RTL code of the key IP is consistent with the gate level netlist logic function after its logic synthesis.(3)SoC integration and hardware-software co-design.In this study,the three key IPs are firstly integrated in SoC,and a software and hardware synergy scheme is also proposed for the efficient control of PMSM by SoC.(4)SoC-level functional verification.In order to verify the basic functionality of the key IPs after SoC integration,this study builds a SoC-level verification platform and introduces UVM verification methodology to improve the efficiency of SoC-level verification.(5)FPGA prototyping.In this study,we use the Vivado tool to synthesise the SoC to obtain the SoC resource consumption and the percentage of resource consumption of key IPs.A three-axis servo control system was also built based on FPGA prototyping platform to test the SoC’s control performance for PMSM.The functional verification and experimental test results not only prove the correction of the key IPs designed in this study,but also demonstrate that the three key IPs designed in this study only need to consume a certain amount of area for integrating to turn a general-purpose SoC into a dedicated SoC for PMSM control,which can drive three motors independently and synchronously with high control accuracy and fast current and speed response.This study makes it possible to efficiently implement single-axis and multi-axis servo control on a low-cost,low-power SoC chip.