Design Of Multi-Phase High-Current Buck DC-DC (Direct Current To Direct Current) Chip

In recent years,with the gradual development of the semiconductor industry,the size of various devices and chips has gradually decreased,while the power consumption of various electronic devices has increased,resulting in a growing demand for power converters in electronic systems.These power converters are required to have higher efficiency,greater output power,and smaller size.DC-DC converters,as a type of circuit that can convert input DC voltage to the required output DC voltage,can provide stable power for electronic devices.In high-current application scenarios,multi-phase parallel technology has become one of the solutions to obtain a greater load capacity by parallelizing multiple DC-DC controllers.However,in the process of multi-phase parallelization,uneven current distribution is a common problem,which may cause some controllers to overload,while others may be underloaded,affecting the stability and performance of the system.Therefore,current equalization technology has become one of the keys to multi-phase parallel technology.The DC-DC chip designed in this paper adopts a new current equalization technology that combines traditional average current equalization and master-slave control.Specifically,the current of each phase is sampled relative to its own inductance current,and the average value of all phases is obtained through a current equalization bus.Then,the inductance current of this phase is compared with the average current,and the output of the common error amplifier is compensated for its own current error,thereby improving the accuracy of current equalization.This design also integrates two-phase DC-DC controllers in one chip,and the pin logic design allows users to choose single-phase output or two-phase parallel output or two-phase independent output,which is very flexible and can effectively save area.This design supports up to 12-phase parallelization,i.e.,6 chips in parallel.It is designed with a clock synchronization pin,and the clock input can be selected from external input and internal generation,and the clock phase of the chip can be flexibly adjusted to achieve parallel interleaving.It has the advantages of flexible use,high adaptability,and wide application.This paper first introduces the background and research significance of the topic,and then introduces the basic principles of synchronous DC-DC,and respectively expounds on phase-locked loop technology and current equalization technology.The newly designed current equalization technology in this paper is explained in detail,and the current inductance sampling module,internal current average module,chip-to-chip current average module,current error compensation module,clock module,phase control module,PWM module,and other modules are analyzed in detail and simulated.This design chip is based on 0.35μm BCD process design and has completed the design and functional simulation of each module on the Cadence software platform using Spectre simulation software.Finally,the chip was verified by overall simulation.