Research On Voltage Synchronous Phase-locking Method In Single-phase Grid Under Non-ideal Conditons

In energy and power applications such as active power filters and distributed generation systems,it is important to obtain information such as phase,frequency,and harmonic components of grid voltages quickly and accurately.Phase-Locked Loop(PLL)consists of a phase detector,a loop filter and a voltage-controlled oscillator.It has a simple structure and is easy to implement,and is widely used in power grid synchronization.Different from the three-phase power supply system,in the singlephase system,since there is only one input signal,the phase-locked loop structure is more complicated.In recent years,the phase-locked loop based on Quadrature Signal Generator(QSG)has played a crucial role in single-phase systems due to its robustness under non-ideal grid voltage conditions.However,when there are harmonics and DC offsets in the grid,the PLL cannot phase lock accurately.Therefore,based on the idea of signal delay,this paper studies how to suppress DC offset and harmonic interference in a single-phase phase-locked loop.The main work is summarized as follows:First,on the basis of analyzing the basic principles and mathematical models of single-phase PLL,the dynamic and steady-state performance are studied in detail.Several common quadrature signal generators are introduced,and it is emphasized that the single-phase PLL will generate phase-locking errors under the harmonic distorted power grid condition,and cannot achieve accurate and fast phase-locking.It provides a theoretical basis for further research on harmonic and DC offset suppression methods.Then,in view of the shortcomings of traditional quadrature signal generators such as slow dynamic response and sensitivity to harmonics,an improved PLL algorithm based on Multiple Recursive-form Generalized Delayed Signal Superposition Operator(MRGDSS)is proposed.In the time domain,the filtering principle and derivation process of the general signal delay-superposition operator are analyzed.In order to reduce the computational complexity and complexity of the algorithm,a recursive implementation of the general signal delay-superposition operator is deduced in the discrete domain.The RGDSS operator can generate quadrature components and filter out unwanted harmonics.The proposed MRGDSS-PLL can effectively eliminate the influence of DC offset and harmonic interference,and obtain fundamental and multiple harmonic information quickly and accurately.Finally,in order to eliminate the influence of DC offset on the PLL synchronization performance,the grid synchronization can be realized under non-ideal conditions,an improved single-phase phase-locked loop technology is proposed based on MRGDSS-PLL.Two types of DC offset suppression methods which are widly used at present are deeply analyzed.On this basis,a DC offset suppression method based on Modified delay signal cancellation(MDSC)is proposed.Then,the anti-noise performance of the proposed MDSC algorithm is studied and corresponding solutions are proposed.The cascaded MDSC and RGDSS operators are used as the pre-filter to design PLL,which is combined with SRF-PLL.The effectiveness of the proposed gridconnected PLL is verified by simulation and experiment.