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Design And Implementation Of Digital Module In CAN Transceiver For Partial Networking

Posted on:2023-10-01Degree:MasterType:Thesis
Country:ChinaCandidate:J PanFull Text:PDF
GTID:2532307103482044Subject:Electronic Science and Technology
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CAN bus has become one of the most widely used bus systems in automobiles after 30 years of development since it was proposed by Bosch in the 1980 s.With the world’s increasing attention to energy conservation and emission reduction,various new energy vehicle policies have been launched,and the heat of new-energy vehicles continues to rise,with "an inch of electricity is an inch of gold" to describe the value of electric energy of new-energy vehicles.To reduce energy waste in vehicle CAN bus systems,NXP Semiconductor(NXP)proposed a partial networking solution in 2012,which can achieve low power consumption of CAN networking through transceivers and realize CAN and CAN FD node compatibility conveniently and cheaply.However,However,there is almost no research on the transceiver for partial networking in the domestic,and domestic automobile manufacturers completely rely on foreign automotive electronics and semiconductor companies.To solve the foreign monopoly of such chips and realize the domestic substitution as soon as possible,this paper is based on international standards ISO11898-6 and ISO11898-2:2016 of CAN bus as the specification.The key technologies for digital circuits in the transceiver for partial networking are studied.Based on ISO11898 and other related CAN bus protocols and standards,and referring to the existing advanced CAN transceiver products abroad,this paper determines the key points of implementing the selective wake-up and CAN FD shielding functions,and puts forward the overall architecture of CAN transceiver for partial networking and the architecture of digital circuit in it.By comparing the difference between CAN and CAN FD frame structures,a CAN FD shield design solution is proposed.Based on the bitstream state jump of the CAN controller,a special bitstream jump is developed to meet the requirement of the transceiver for partial networking.In the RTL stage,Verilog HDL was used to design the front end of the whole digital circuit,and the function was successfully simulated.Since the transceiver for partial networking needs a low power consumption mode,four modes of shutdown mode,working mode,idle mode,and sleep mode are designed to meet the application requirements of different scenarios.Flexible switching can be carried out through the SPI interface.In the SPI slave interface,an asynchronous cross-clock domain design is adopted to meet the higher rate of serial communication in the case of low main frequency and to reduce the dynamic power consumption of the whole digital circuit.In addition,the design of digital circuits in RTL level,gate level,and back-end physical implementation of low power processing.The back end is based on the domestic 180 nm process to complete the digital circuit layout.Finally,according to the power analysis,the power consumption of the whole digital module in low power mode is only 152.65 μW,and the layout area of the digital circuit is 472644 μm~2.The final test results show that SPI can successfully access internal registers and flexibly switch transceiver modes,and the functions of selective wake-up and CAN FD shielding are normal.The communication rate of the SPI slave interface is up to 1 Mbps.The highest CAN communication rate supported by selective wake up is 1 Mbps and CAN successfully wake up the device;Sending CAN FD frames CAN achieve effective shielding.The important functions in the digital module are realized,and the testing results of a tape-out meet the expected results.
Keywords/Search Tags:CAN transceiver, Selective wake-up, CAN FD shielding, Low power design
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