Design And Implementation Of A Zynq SoC Deep Learning Accelerator For Drone Image Recognition Task

With the rapid development of UAV technology,especially the rise of various multi-target,multi-source and high-resolution aerial photography data,human beings have created a large amount of aerial photography data.It is precisely because of the complexity and diversity of data sets that the detection tasks that could not be completed due to data constraints can be realized at this stage,which promotes the continuous research and exploration of technology in the field of target detection to meet the growing needs.The feature extraction and learning ability of neural network provides an efficient and convenient means for the target detection and recognition task of UAV image.The mainstream target detection methods based on deep learning,such as Yolo series and RCNN series networks,can process and predict UAV data efficiently.However,the real-time recognition of UAV image data requires sufficient hardware environment,such as the use of multiple high-performance GPUs,which limits its application in UAV image real-time detection task.Moreover,the main concern of most researchers is to optimize the neural network structure,and few researchers study the real-time performance of target detection in the field of limited power consumption.Therefore,this paper proposes to study the real-time target detection in the environment of low power consumption and low energy consumption from the two levels of software and hardware.At the software level,the yolov5s network with low computation and low network layers is used for the network training task of UAV data set,and the 8-bit dynamic quantization is carried out to further reduce the total parameter he computation.At the hardware level,the research and development of neural network accelerator based on the network is carried out.In order to enhance the parallelism and efficiency of hardware,a frequency doubling cascade DSP design scheme is designed as the core computing unit of convolution computing.At the same time,the accelerator structure also realizes multi-scale design,pipeline design and multi module design,which reduces the resources and power consumption of FPGA to a certain extent.The experimental results show that the proposed solution uses zynq-mz7100 fa to achieve about 1.2tops per second under the 200 MHz master clock,with a power consumption of 16 W.It can process visdrone data sets in real time and efficiently.The map reaches 27.1%,and the recognition speed reaches 76 frames per second.