| Ferroelectric-based electrostatically doping technology（Fe-ED）,an promising doping technology,stems from the ferroelectric spontaneous polarization and electrostatic bias doping technology.It possesses tremendous merits,like low thermal budget,free-impurity,accurate control for the concentration,type and spatial distribution,especially for the non-volatility and reconfigurability,which provides many opportunities for future nano-electronic devices.In this dissertation,we comprehensively investigated the design principle of Fe-ED Fin FETs for the performance optimization.The main contents are as the following:1.The study on electrical characteristics and design principles of Fe-ED Fin FET devices We simulated the electrical characteristics of Fe-ED Fin FETs based on TCAD Sentaurus tools,where the ferroelectric polarization behavior is described by Preisach model.It is demosntrated that Fe-ED exhibits both programmability and non-volatility,contributing to the reconfigurable n/p type Fe-ED Fin FETs.Additionally,Fe-ED with the accurate control of doping profile,produces a spontaneous lightly doped drain structure（LDD）,which greatly suppresses the short-channel effect of the device,facilitating the improved sub-threshold characteristics and drain-induced barrier lowering（DIBL）characteristics compared to the reference device.The impact of ferroelectric properties and structures on the electrical performance of Fe-ED Fin FETs was also investigated,aiming at revealing the design principle of Fe-ED Fin FETs for the performance optimization.It is demonstrated that the best doping effect can be achieved by using the surround ferroelectric layer distribution,which can significantly improve the Ion of the device.There is an intermediate optimal value for the selection of ferroelectric layer thickness and polarization voltage to achieve a more balanced electrical characteristics of the device.By increasing Pr and Ec,the carrier concentration induced by the polarization gate in the S/D region can be increased,which can improve the Ion.On the other hand,the short-channel effect can be significantly degression by increasing LG,and the DIBL and SS of the device can be optimized by using appropriate Fin thickness or increasing Lsp.Finally,the fermi level pinning effect of Fe-ED Fin FET device is studied,and the limitation of the on-state current is mainly due to unregulated schottky barrier of device which is related to the fermi level pinning effect of S/D contact.2.The investigation on optimization of source-drain contact engineeringThe comparison study of the electrical properties of Fe-ED Fin FET with different contact engineerings of metal-semiconductor（MS）and metal-insulator-semiconductor（MIS）were performed.It is found that the fermi level pinning effect can be effectively removed with the inserted insulator layer,and the S/D Schottky can be adjusted via the workfunction engineering at S/D contacts.Higher device on-state current and improved SS characteristics can be achieved while maintaining the advantages of DIBL by lowering the Schottky barrier.Through the investigation of insulator layer parameters in MIS contact,it is demosntrated that smaller thickness,lower?,smaller tunneling mass and lower band offset of the insulator layer can improve the carrier transport efficiency,which increases the on-state current of the device.Through the comprehensive optimization of the insulator layer material of MIS contact,almost one order enhancement in on-state current can be achieved for both n/p-type devices with MIS contacts over the counterparts with MS contacts.In summary,we established Fe-ED Fin FET device model and investigated electrical characteristics simulation.Then we studied the optimization mechanism of contact engineering on the electrical characteristics of the device.It broadens the application range of ferroelectric materials in transistors,and lays a foundation for the research of logic operation unit,processing in memory and non-volatile memory based on Fe-ED devices. |
