Research On Thermal-mechanical Reliability Of 3D Stacked Packages For Ultra-thin Memory Chips

The advancement of microelectronic packaging technology has led to higher expectations for memory packaging.The emergence of three-dimensional packaging technology can integrate multiple functions into one package,reducing package volume and increasing package integration,and it is extensively used in memory packaging,epoxy encapsulation materials have certain mechanical limitations that can result in reliability issues like chip warping and interface delamination,especially during the post-curing process.In practical use,the high junction temperature and warping risk brought by chip power consumption also need to be considered.This study focuses on the interlaced threedimensional packaging structure of ultra-thin storage chips as the research object.The reliability of the packaging is investigated during the production process and in-service state by utilizing a combination of simulation and experimental characterization.In order to account for the viscoelastic behavior of epoxy encapsulation materials,a simulation model utilizing the advanced finite element software Ansys has been developed.The research presented in this paper encompasses the following specific topics:(1)The mechanical properties of epoxy encapsulation materials during the post-curing process are characterized based on the generalized Maxwell equations.To obtain temperature and frequency dependent viscoelastic parameters such as storage modulus,loss angle,and glass transition temperature,dynamic mechanical experiments are conducted.The results of this study provide valuable insights into the behavior of these materials under varying conditions.The storage modulus master curve is processed using the generalized Maxwell equations based on the time-temperature superposition principle.This allows for the determination of other viscoelastic parameters such as shear relaxation modulus,bulk relaxation modulus,and more,which can be utilized for simulation purposes.Through thermal-mechanical analysis experiments,the deformation-temperature curve of the epoxy encapsulation material is obtained,and the glass transition temperature is detected as well.Additionally,a linear fitting method is employed to determine the thermal expansion coefficient of the material.These findings contribute to a better understanding of the material’s behavior and can inform the development of improved encapsulation materials.Through the thermal conductivity experiment,the thermal conductivity and other parameters of epoxy sealing material were obtained.(2)A three-dimensional stacked packaging model for ultra-thin storage chips is established,taking into account the viscoelasticity of the epoxy encapsulation material.Based on finite element analysis,the change in warpage during the post-curing process is studied,and the effect of post-curing temperature on packaging reliability is explored.The study shows that with the increase of post-curing temperature,the peak value of storage chip warpage increases,and the equilibrium time is longer.The warpage of the chip also increases with the equilibrium time.Through Taguchi orthogonal experiment combined with range analysis,the structure of the stacked packaging module is optimized.The influence of each experimental factor on the packaging warpage is as follows:encapsulation thickness > bonding layer thickness > chip thickness.After optimization,the warpage value of the chip stack module is 27.186μm.(3)A thermal-mechanical coupled analysis is conducted on the three-dimensional stacked packaging of ultra-thin storage chips to study the junction temperature and warpage of ultra-thin storage chips under normal working conditions,and to optimize the packaging structure based on these factors.Weighted analysis of the orthogonal experimental design results was used to study the influence of each structural factor on the packaging reliability.The results show that warpage deformation and high junction temperature are important issues affecting the reliability of the three-dimensional stacked packaging of ultra-thin storage chips.The thickness of the EMC and DAF layers has the most significant impact on chip warpage and junction temperature.As the thickness of the EMC layer increases,chip warpage and high junction temperature are significantly improved,followed by the thickness of the DAF layer.According to the weighted analysis of the range analysis results,the influence of each structural factor on chip warpage is:EMC thickness > DAF layer thickness > Chip thickness.The optimized structure is:Meeting the packaging reliability standards,the epoxy molding compound has a thickness of 0.9mm,while the storage chip and chip adhesive layer have thicknesses of 70μm and20μm,respectively.In summary,this article provides a preliminary exposition on the impact of process parameters and component structure on the reliability of ultra-thin storage chip stacked packaging under post-curing process and normal operating conditions.The aim is to provide some guidance for packaging design and related reliability research.