Design Of Computing-in-Memory Circuits Based On Polymorphic Spintronics Devices

The "memory wall" bottleneck faced by traditional Von Neumann architecture in storing and computing massive amounts of data has led to an increasing interest in the research of computing inmemory systems.Among them,the implementation scheme based on magnetic random access memory(MRAM)has gained significant attention due to its advantages such as low power consumption and non-volatile resistive state.However,the storage core of MRAM,the magnetic tunnel junction(MTJ),can only store two states,high resistance and low resistance,and cannot achieve multi-bit data storage,which limits the storage and computing efficiency of MRAM-based computing in-memory systems.Therefore,we present a single-device multi-bit in-memory computing system based on a new type of spintronic device,the Hall-Bar.To address the small output anomalous Hall voltage of the Hall-Bar,this thesis focuses on circuit design and undertakes the following work:(1)Establishing an electrical model of the device.Based on the characteristics of the Hall-Bar and sample data,the structure and size of the Hall-Bar and the electrical signal input scheme used in thesis are determined.Using the hardware description language Verilog-A,an electrical model of the device is established,and is verified through model simulation.(2)Proposing a system framework for in-memory computing design based on polymorphic spin electronic devices.Taking the Hall-Bar storage-computing integrated characteristic as the core,a technology scheme is adopted for the first time in which the convolution operation is completed in the Hall-Bar array in the form of analog circuits.The full-bridge circuit is designed to provide write current pulse drive;and the two-stage folded-cascode amplifier is designed to amplify the high-bias micro Hall voltage signal.The current-mode DAC is further designed to generate multi-bit accurate read current,and finally,the adder circuit is designed to match the Hall-Bar array for multi-bit multiply-add operations.(3)Simulating the peripheral circuit performance under the SMIC 0.18 μm process.Under the process corner of TT and temperature of 27 ℃,the two-stage folded-cascode amplifier achieved a high open-loop gain of 85 d B,phase margin of 76°,common-mode rejection ratio of 127 d B,loop phase margin of 73°,and common-mode input range of 0-3.5V,with system offset and random offset voltages of 1.6 μV and 41 μV,respectively;the output current range of the current-mode DAC is 1.01 m A to 8.96 m A,with an LSB current of 31.3 μA,DNL and INL within 0.5 LSB and 1 LSB,respectively,indicating good linearity and SFDR is 35 d B at sampling frequency of 1 GHZ.(4)Performing joint simulation of the Hall-Bar model and other peripheral circuits.The error between the final output result of the 1×2 convolution operation module and the theoretical value is0.4%,successfully verifying the in-memory computing characteristic of the Hall-Bar device,and proposing a highly integrated and expandable storage-computing integrated array architecture.This thesis verifies the feasibility of the multi-valued in-memory computing scheme based on the Hall-Bar for integrated circuit development through simulation,and provides a new technological path for multi-valued storage-computing and neuromorphic computing chip development.