Font Size: a A A

Development Of DC Polarometer Receiver Based On ARM+FPGA

Posted on:2023-04-05Degree:MasterType:Thesis
Country:ChinaCandidate:X B LuoFull Text:PDF
GTID:2530307070487754Subject:Engineering
Abstract/Summary:PDF Full Text Request
Direct current polarization method is an important geophysical exploration method to detect metal sulfide ore.However,with the increase of detection depth,the polarization field signal becomes weaker and weaker.In order to extract useful IP signal,it is urgent to develop highprecision IP instrument.Based on the above background,this paper analyzes the development status of Polaris at home and abroad.Based on ARM+FPGA,The receiver of DC Polaris is designed by field programmable logic gate array.Firstly,the signal conditioning part,through the design of preamplifier,input protection circuit,natural potential compensation circuit,active low-pass filter circuit,single-end to double-end circuit,select 32 bits ∑-Δ type ADC to carry on the analog-to-digital conversion of the signal,to ensure the signal-to-noise ratio of the collected data;Secondly,the power supply part of the system is designed,and the distributed architecture is adopted.The first stage uses DC/DC converter to efficiently convert the input power,and the last stage uses low-voltage differential linear voltage regulator to provide high-precision voltage for the device.Control system based on Micro Zed development board for synchronous sampling and storage of 6channels of data,digital to analog converter,battery voltage monitoring,acquisition circuit magnification,clock synchronization system control,and design a clock source circuit to provide high precision clock signal for the system.In this paper,Altium Design20 was used to design the circuit schematic diagram,draw the PCB board,produce the acquisition card and backplane,and assemble the prototype.By using dynamic signal analyzer and spectrum analyzer,the simulated front-end circuit noise,frequency response and common mode rejection ratio are tested.The test performance indexes are as follows: When the equivalent input noise density is 78.1n V/(?) 1Hz and 12.1 n V/(?) 100 Hz,the circuit cut-off frequency is1 k Hz,and the circuit gain is 10.5d B,the CMRR is 105 d B.When the circuit gain is 0d B,the CMRR is 95.5d B.The 6-channel synchronous test and polarization test were carried out on the prototype,which verified that the6-channel synchronous acquisition could be carried out without deviation,and the correct potential information could be collected.The experimental results show that the dc IP receiver designed in this paper has the characteristics of low noise,high CMRR,high stability,high precision and large dynamic range,which can be applied to field exploration and successfully completes the design task.
Keywords/Search Tags:Dc IP receiver, Low noise, Multi channel, ARM+FPGA
PDF Full Text Request
Related items