Research On The Peripheral Digital Circuit Of The Key Detector Prototype Chip For Heavy-Flavor Tagging In Higgs Physics At CEPC

In 2012,CERN discovered the Higgs boson in the Large Hadron Collider experiment,and the field of particle physics entered a new era.Exploration of new physics beyond the Standard Model by precisely measuring the properties of the Higgs bosons has become a hotspot in the field of particle physics.Based on this,Chinese scientists proposed the Circular Electron-Positron Collider(CEPC)program to fabricate a large number of Higgs bosons for research.At present,the CEPC program is still under preliminary research.This is an opportunity of fundamental physics of China.The Higgs bosons are extremely unstable and decay rapidly after being produced.The separation of different decay channels is very important for the study of the Higgs bosons,which requires a vertex detector of high resolution to achieve flavor tagging of the decay products effectively.The vertex detector of CEPC is the detector closest to the reaction point,requiring high spatial resolution,fast readout,low material budgets and good radiation resistance.Monolithic Active Pixel Sensors(MAPS)can meet all the requirements.The development of silicon pixel detectors abroad is relatively rapid,and there is still a large gap between Chinese technical level and the international frontier.At present,none of the silicon pixel detector chips independently developed by Chinese can meet the requirements of the CEPC vertex detector,but this is a hurdle that must be overcome in the development of silicon-based chips in China.In the MAPS chip,the readout speed determines the detector chip’s ability to detect particles.A fast readout architecture is important for the MAPS chip to complete the detection task.This is also a key technology that must be mastered in independent research and development of silicon pixel chips in China.Based on the research and development of the CEPC vertex detector prototype chip,this thesis focuses on the readout speed and searches for a readout architecture that can meet the requirements of the CEPC vertex detector.The main work of this thesis is to participate in the design of the CEPC vertex detector prototype chip MIC5,and propose a peripheral digital circuit structure that may be applied to the CEPC vertex detector MAPS chip.The structure is analyzed and based on the TowerJazz 180 nm CMOS Image Sensor process,with the readout speed of 800 Mbps and power consumption of about 80 mW.The main work of this paper is presented in the following aspects:1.At present,there is no mature and systematic theoretical research on the digital readout architecture for the peripheral circuits of MAPS chips at home and abroad.This paper independently designs a peripheral readout architecture that does not require onchip RAMs,designs a two-level cache structure based on FIFO,and analyzes it.The relationship between its feasibility and the setting of FIFOs’ depth and the pixel hit rate and readout speed,at the same time,a new data management and data frame structure is designed,which not only ensures that the information of the hit pixels can be completely recorded and transmitted,but also matches the data readout rate of the chip,and achieve the optimal solution for the current situation.2.Based on the TowerJazz 180 nm CMOS Image Sensor process,this paper completes the design of the physical layout of the peripheral digital circuit according to the digital integrated circuit design process,and verifies the function and performance of the MIC5 peripheral digital circuit through physical verification of the layout and post-layout simulation.3.This paper designs a hardware test system for the peripheral digital circuit of MIC5 based on FPGA,and tests functions such as SPI control and data readout,which verifies the correctness and operability of the design of the peripheral digital circuit of MIC5,and lays the foundation for the chip testing in the future.