Research On Error Correction Key Technologies For Continuous Variable Quantum Key Distribution Based On FPGA

With the uninterrupted evolution of modern information technology,the information security issues are becoming increasingly crucial.Ensuring the security of information transmission is needed in the aspect of national stability,enterprise development,and personal privacy.Quantum key distribution can provide unconditional security for quantum secure communication.Continuous variable quantum key distribution is an important branch of QKD,which is characterized by low cost.In CV-QKD system,error correction is a very important step in post-processing.The legitimate parties need to use error correction codes to correct the different bits in the bare codes.Parallel calculation can be used to speed up the process of error correction.As a mature and highly integrated implementation platform,FPGA’s powerful parallel computing ability just meets the needs of error correction process.LDPC code is a kind of high performance errorcorrecting code.This paper mainly studies the layered decoding algorithm of LDPC code with low bit rate and long code length based on FPGA hardware acceleration technology.The main work is as follows.1.According to the whole process of LDPC layered decoding algorithm,it is divided into three main steps:information preparation,iterative calculation and decoding decision.Information preparation needs to solve some problems such as storing the posteriori probability(including initial information),check nodes information,syndrome,the columns of nonzero submatrix in base matrix and the offset value.This paper assigned the column information of the same submatrix to the same address of different RAM,combined with the row weight,This method sharply reduce the consumption of storage resources.Iterative calculation is to instantiate multiple instances to form different branches to complete variable node update,check node update and posterior probability update in parallel according to column number and offset value information.According to the nature of the function ψ(x),a two-stage lookup table is adopted to reduce the complexity of its hardware implementation.The depth of the first section is 256,and the depth of the second section is 64.The decoding decision process is carried out in layers to avoid the problem of too large bit width when using complete syndrome to participate in comparison.2.In this design,the method of data parallelism and pipeline division is used to improve the processing speed,and the module TDMA is adopted to reduce the resource consumption of FPGA.Finally,this paper realizes the LDPC layered decoding algorithm of LDPC codes with code length of 100K and code rate of 0.1 and 0.2 on FPGA platform,generates keys,and carries out simulation tests on each sub-module and the overall module to verify its function and timing.When the reconciliation efficiency is 93%,the throughput is 10.05M symbol/s and 68.76M symbol/s,and the overall resource ratio of the algorithm to the selected FPGA is about 3/4.