Research And Design Of SAR ADC For Bioelectric Signal Acquisition

People can effectively monitor the changes of human physiological signals through the human body electrical signal acquisition system,which can realize the prevention and control of diseases.As the core module in the overall acquisition system,ADCs are moving towards greater accuracy and lower power consumption.In order to reduce the design difficulty of the ADC front-end analog circuit and reflect the characteristics of physiological electrical signals more accurately,the use of low-power and high-resolution ADCs will make the entire system perform the best.The main work of this paper is to design a low-speed SAR ADC with low power consumption and high resolution according to the performance requirements of the physiological signal acquisition system.The traditional N-bit SAR ADC based on capacitive DAC structure is limited by non-ideal factors such as quantization noise and comparator noise when achieving high precision,and the number of capacitors in the DAC increases by2~N.These factors lead to the energy efficiency of high precision SAR ADC very low.In order to reduce quantization noise and comparator noise,this paper first proposes a direct integration type first-order noise shaping circuit,which reduces the noise in the signal band by 16.5dB at low frequencies.The equivalent input noise of the comparator is reduced by96.8%after plastic surgery.Compared with the traditional noise shaping structure,the proposed structure eliminates the residual sampling capacitance,reduces the k T/C noise and signal attenuation on the integration path,and does not require a comparator on the integration path to provide gain compensation,thus reducing the power requirements.In this paper,a low-power and high-precision low-speed SAR ADC designed using a180 nm CMOS process is validated by circuit simulation and layout design.The post-simulation results show that with a sampling frequency of 400KHz and an oversampling rate of 32,the final effective bit count is 14.56 bits,an SNDR of 89.43dB,an SFDR of 94.41dB,a power consumption of only 10.2uW,a quality factor(Fo M)of 177.3dB and a whole ADC core area of 0.238mm~2.