Design And Implementation Of Security Chip Based On National Secret Algorithm

With the continuous development and progress of the Internet of Things,more and more users use the Internet of Things.How to protect the user's information security has become one of the important research topics in the field of Internet of Things technology.Because the national secret algorithm has the characteristics of security,integrity,non-replicability,etc.,the security chip containing the national secret algorithm module has a wide range of application prospects and needs in the Internet of Things and other fields.Therefore,in view of the security problems of users in the field of information interaction such as the Internet of Things,this paper completes a security chip design based on the national secret algorithm based on the 55 nm process standard cell library of SMIC.The main contents include:Firstly,the encryption and decryption speed and hardware resource usage of several typical cryptographic algorithms in the development process of cryptography are compared and analyzed,and it is concluded that the cipher strength of elliptic curve algorithm is higher.my country's commercial cryptographic algorithm SM2.Next,the principle of the national secret algorithm is analyzed,the concepts and operations of elliptic curves and finite fields are introduced,and the theoretical basis and parameter definitions are provided for the subsequent design of the national secret algorithm.Secondly,using the verilog language,the system architecture design of the national secret algorithm is completed,including the function implementation layer,point operation layer,and modular operation layer in the hardware architecture.In the aspect of operator design,the specific implementations of point multiplication,multiplication,modular addition,modular subtraction,modular multiplication,and modular inverse operations are described.Finally,the verification of the design of the national secret algorithm module is completed.The front-end functional verification of the module is carried out using UVM environment,and then the design is logically synthesized in the 55 nm standard process library,and the netlist is generated after synthesis,and the back-end simulation verification is carried out.After the layout and routing,the digital layout was generated,and then the specific functions of the national secret algorithm were verified by FPGA and the finished chip test after tape-out.The simulation verification and test results show that the national secret algorithm can complete functions including dot multiplication,digital signature and digital signature verification,and the digital signature can reach an average speed of 489 signatures per second at a clock frequency of 80 MHz,which is in line with the application of chip design.and work scenarios.The design results of the national secret algorithm this time show that the application of the national secret algorithm module in the security chip can correctly encrypt and decrypt data and information in the fields of the Internet of Things and other fields.