Super Resolution DOA Estimation And Hardware Implementation Of Millimeter Wave MIMO Radar

Direction of arrival(DOA)estimation of multiple input multiple output(MIMO)radar is of great value in the fields of battlefield target location and tracking and vehicle assisted driving.The DOA estimation performance of direct digital beamforming MIMO radar is limited by the quantity of antenna elements.In consideration of the space,the cost and other factors in practical engineering,there are many limitations in the method of improving the resolution performance by increasing antenna elements.Instead,combining with the existing hardware,super resolution DOA estimation algorithms could obtain a higher accuracy than direct digital beamforming by improving the method of signal processing.It can solve the problems caused by the limitation of the cost,the space,and the performance.However,the existing super resolution depends much on enormous amount of snapshot and is companied with complex calculations.Thesis aims at the problems of few snapshots and real-time signal processing of MIMO radar super resolution DOA estimation.The main contents are as follows:1.Thesis studies the super resolution algorithms of MIMO radar equivalent virtual array model,and the influence that caused by different signal to noise ratio and snapshots to the accuracy of super resolution DOA estimation algorithms.2.According to the features of FPGA platform,thesis improves the fast iterative adaptive approach(IAA-Fast)DOA estimation algorithms.Besides,efficiency of the algorithms is improved by the application of concurrent design.3.Thesis puts forward a hardware architecture to practice the IAA-Fast resolution on the FPGA platform,optimize the algorithms on the level of hardware,design the key steps in the algorithms in modularization,and provide the schemes of optimizing the resource and the time-consuming.4.The above methods are implemented and verified on Xilinx XCZU9 EG FPGA.According to the actual data of MIMO radar with 2 transmitting and 4 receiving antennas,in the 256×256(range×angle)scenario,the retardation is as low as 8.197 ms when invoking 4 concurrent modules to complete 6 iterations.