Research On Verification Sequence Generation Technology Based On UVM Verification Platform

With the rapid development of the information industry,chips have gradually become a shortcoming restricting the development of various industries.Ensuring the functional correctness of the chip has become an important issue in the current chip field.Functional simulation verification uses different verification sequences to verify the functional correctness of the design.It is the first line of defense to ensure chip security.However,the current verification sequence generation technology will generate a large amount of invalid data,which will reduce the verification efficiency and slow down the chip project.This paper uses UVM(university verification methodology)to build a verification platform,and studies the verification sequence generation components in the platform.The main work is as follows:(1)An improved coverage-driven verification method is proposed,the verification plan is integrated into the coverage-driven verification process,and an effective verification sequence is generated based on the feedback information of the verification plan to ensure the completeness of the overall verification work.By analyzing the generation process of the verification sequence set,the actual problem is abstracted and modeled as a constraint satisfaction problem,and a hybrid Firefly Algorithm is proposed to solve the problem.In the algorithm,the standard Firefly Algorithm is designed as a global convergence strategy,and for its shortcomings of premature convergence,a local search strategy based on Tabu Search is proposed to enhance its local search ability,and then the corresponding objective function is designed to calculate the individual.Finally,the standard test function is used to test the convergence performance of the hybrid Firefly Algorithm and the standard Firefly Algorithm.(2)Based on the actual engineering project,a verification plan was developed for the APB(Advanced Peripheral Bus)-I2C(Inter-Intergrated Circuit)bus protocol conversion module in the project,and the main functional points to be verified of the design were classified and summarized.And based on the UVM verification methodology,a corresponding simulation verification platform was designed,and then the main functional test scenarios of the design were simulated and tested,and the verification sequence generation results integrated into the hybrid Firefly Algorithm were compared with the standard Firefly Algorithm and randomly generated results.It is found that the verification platform using the hybrid Firefly Algorithm can use fewer verification sequences to achieve higher coverage under the same conditions,the algorithm converges faster,and the scale of the generated verification sequence set is also smaller.