Design Of Key Circuits Of Charge Pump Phase-Locked Loop

With the continuous progress of semiconductor technology,transceiver chips can support a variety of communication protocols,which cover a wide frequency range.In order to have the capability of multi-protocol communication,devices often install several transceiver chips that work at different frequencies.This method not only squeezes space and raises costs,but also require chips to have high compatibility.This thesis provides a single-chip solution from the perspective of local oscillator.Key modules in charge pump phase-locked loops(CPPLL),including phase frequency detector(PFD),charge pump(CP),loop filter(LPF)and voltage controlled oscillator(VCO)are analyzed and designed.This thesis adopts the top-down approach,starting from the loop structure,model and performance of the phase-locked loop,analyzes the constraints between key modules,determines key design parameters,and then goes deep into each module to analyze the specific circuit design,including device selection,nonidealities and performance optimization.A broadband and low gain VCO is designed.The mathematical relationships between the key indicators of the VCO,including tuning range,gain,overlap range and number of bands,are derived.A 9 bit capacitor array is used for coarse tuning and a single set of varactors is used for fine tuning.A variety of phase noise optimization techniques are used.The measured VCO gain is less than 80MHz/V,the tuning range is 6.13GHz?12.37GHz,the phase noise@1MHz of the whole range is-111d Bc/Hz?-119d Bc/Hz.A Fo M_T@1MHz of 194.7d B?199.5d B is achieved.The PFD and the CP designed in this thesis have the characteristics of high speed and low mismatch,and the linear detect range without dead zone reaches-354°?354°.In order to adapt to the extremely wide tuning range of the PLL,the charge/discharge current of the CP is adjustable in 3 bit.An error amplifier is used in the charge pump to suppress the channel length modulation effect,and a variable capacitor is added to speed up the switching of CP states.The static mismatch and dynamic mismatch of the CP are both very small.Within the output voltage range of 0.1V to 1.1V,the static mismatch is less than 1%of the total charge/discharge current.A design method of a third-order passive loop filter is presented.The design method for loop parameters such as loop bandwidth and phase margin is analyzed from the perspective of the noise contribution of modules.The relative bandwidth of this PLL is over 67%,and has been taped out and measured.The measured RMS jitter of the PLL is 442fs.The PLL achieves a Fo M_T of 245.1d B?246.7d B with a power consumption of 50m W?73m W.