Design And Implementation Of HDR Image Fusion Algorithm Based On FPGA

With the increase in the resolution,frame rate,and quality of digital images,as well as the increase in the integration of digital image systems,High Dynamic Range(HDR)image technology has become a research hotspot in the image field.It has been widely used in medical,aerospace,security monitoring,intelligent electronic equipment,game special effects,etc.,and has strong practicability.The dynamic range of common image sensors is quite different from the dynamic range of natural ambient light or brightness that can be discerned by the human eye,resulting in overexposure and underexposure in the acquired images,loss of image details,poor visual perception.Therefore,various technologies to restore high dynamic range scenes have been produced.Often by changing the exposure time,multiple image sequences of the same scene are obtained,then the image sequences are processed by algorithms and synthesized to obtain high dynamic range images.This thesis focuses on the problem of brightness inversion,introduces a guided filtering algorithm,and proposes an HDR image synthesis algorithm based on multiple exposure technology to obtain images with HDR image characteristics.And a simplification scheme for the hardware design of the algorithm in this thesis is proposed.In this thesis,three quality factors of the image — contrast,saturation,and brightness — are extracted as initial fusion weights,and different assignments are given to them so that the brightness quality factor occupies a larger proportion of the initial fusion weight.And modifying the well-exposure curve to reduce the brightness inversion problem in the fusion result;The segmented mapping method is adopted to simplify the calculation logic of the saturation factor,and then the problem of abrupt transition areas is solved;Use the daisy chain structure of the line buffer module to store part of the data in the calculation process;Introduce a lookup table to simplify the calculation of the index in the brightness factor and the division calculation in the normalization;Use shift comparison method,a divider is designed;Pipeline design is added to the computationally complex part of the entire algorithm,and the logically complex operations are processed hierarchically,which improves the overall operating speed.The behavioral simulation of the hardware design of this thesis is carried out.The fixed-point calculation results of Vivado software are basically the same as the floating-point calculation results of MATLAB software.Using Xilinx's Nexys4 DDR board,an FPGA(Field Programmable Gate Array)verification platform is built and the algorithm in this thesis is verified.The verification results show that the maximum operating frequency of the hardware design of the high dynamic range image synthesis algorithm in this thesis is 83.3MHz,which meets the real-time design requirement.