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Design Of Support Vector Machine Accelerator Based On Reconfigurable Computing Platform

Posted on:2022-02-13Degree:MasterType:Thesis
Country:ChinaCandidate:R SunFull Text:PDF
GTID:2518306725490644Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the development of artificial intelligence technology,the demand for efficient and flexible machine learning chips is increasing.Support vector machine is a widely used machine learning classification algorithm,but its computational complexity is high and training efficiency is low.This paper proposes a high-performance support vector machine hardware accelerator based on a reconfigurable computing platform.The training and inference of the algorithm are accelerated by hardware implementation employing parallel computing and pipeline processing techniques.At the same time,efficient resource sharing is realized through the use of reconfigurable computing.The implementations of the training accelerator and the inference accelerator of the least square support vector machine(LS-SVM)are based on a coarse-grained reconfigurable platform,in which the kernel function can be configured.Configurable exponential calculation module,power calculation module based on Table-Driven Taylor expansion method,multiplication and accumulation module,value updating calculation module,update and threshold judgment module and multiplication and accumulation tree module are included.The above hardware modules reuse the computing array in a reconfiguration method,and reduce overall hardware resource usage,and improve resource utilization.At the same time,the parallel and pipeline implementation of the above modules can greatly reduce the computing time,and support any number of samples and feature numbers,which has good flexibility.Finally,functional verification is carried out based on UVM simulation platform and FPGA platform.The synthesis results based on the SMIC 14 nm CMOS process show that the maximum clock frequency after synthesis can reach 1GHz;FPGA implementation based on Xilinx XCVU440 development board can reach the maximum clock frequency of 200 MHz,and some commonly used linear separable and inseparable data sets were tested,and good classification results were achieved.At the same time,compared with state of the art related works,the accelerator can reach 2.1 to 5.9 speedup.
Keywords/Search Tags:Reconfigurable Computing, Support Vector Machine (SVM), Least Squares Support Vector Machine(LS-SVM), Hardware Acceleration, Parallel Computing
PDF Full Text Request
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