Implementation And Application Of Improved K-means Algorithm Based On FPGA

In recent years,the network age is evolving rapidly,and network intrusion detection is gaining a great deal of interest as an essential defence technology in data mining.The K-Means clustering algorithm has enormous capacity for network intrusion detection,because of its simple theory and high performance.However,as the development of the field,higher requirements for the accuracy and speed of intrusion detection are required.The original K-Means no longer meets the practical needs and often requires excellent improved algorithms.In addition,the FPGA platform not only has rich logic resources and supports flexible design,but also has the advantage of parallel data processing,making it popular in the field of accelerating computation.For the difficulties of identifying the initial clustering center points and the uncertainty of the K value,this work uses the density peaks clustering technique to increase the algorithm's accuracy and speed.Furthermore,design and implementation are applied on the hardware description language of Verilog HDL,which based on the FPGA platform.To begin with,an enhanced strategy of the K-Means combined with density peaks clustering is implemented based on thorough examination and understanding of the concepts and principles behind both algorithms.Experimental comparisons are used to verify the modified algorithm's performance in terms of clustering effectiveness and operational efficiency.Secondly,on the basis of the improvement strategy,a global framework for the hardware implementation is proposed,which includes the data input of USB interface,the implementation of density peaks clustering algorithm and the implementation of K-Means algorithm.Finally,the validation of the each functional module is done through Modelsim simulation.Applying the hardware framework of the above improved algorithm to the field of network intrusion detection,for which the classical dataset NSL-KDD is processed by data processing,including one-hot encoding and normalization,and the feature dimension reduction by principal component analysis and genetic algorithm respectively.On the one hand,the impact of redundant features on the network intrusion detection rate is excluded;On the other hand,the reduction of data dimensionality leads to a drop in computational complexity and a consequent lifting in speed.Finally,the modules are deployed on the DE2-115 demo board for testing.The improved K-Means algorithm by density peaks clustering based on FPGA obtains 73.5% detection rate on network intrusion detection and achieves up to 2x than the Intel Xeon processor.In addition,the power consumption of the framework is about one-third of the CPU.