FPGA Implementation And Optimization Of Adaptive Algorithm For Phased Array Radar

Radar plays an important role in war.Pulse phased array radar has become the top priority with its excellent concealment performance and anti-jamming ability.In the field of signal processing,radar anti-jamming technology and research continue to advance,and more and more theoretical results are transformed into engineering realization.The adaptive sidelobe cancellation of pulse phased array radar is taken as the main research object,combined with actual cooperation projects,researches and analyzes the methods of digital beamforming,adaptive sidelobe cancellation and matrix inversion,and formulates the implementation plan.At the same time,the algorithm and function realization of the adaptive sidelobe cancellation processing board are completed according to project requirements and design planning.The array signal model and the digital beamforming algorithm is introduced in the theoretical analysis part.On this basis,the principle of adaptive sidelobe cancellation is introduced,including the minimum mean square error criterion,the maximum signal-tonoise ratio criterion and the linear constraint minimum variance criterion.The analysis of the open-loop algorithm under the minimum mean square error criterion is focused,the influence of the number of samples,interference direction,interference intensity is obtained,and interference quantity on the cancellation effect.In order to solve the optimal weight vector,the commonly used matrix inversion methods are studied,including adjoint matrix inversion,Gaussian elimination inversion,and adjoint matrix inversion.Aiming at the FPGA implementation of elimination method to find the inverse matrix,an optim.ization scheme based on Cordic algorithm is proposed.The position of the adaptive sidelobe cancellation processing board in the radar machine and the system design framework of two FPGAs on the processing board is introduced in the engineering realization part.For testability,the board has channel test and pattern test modes.In addition,the board has auxiliary functions such as channel calibration,frequency point monitoring,and sidelobe cancellation.The link self-synchronization function greatly improves the convenience of board testing,and the system self-reset function increases the board stability.Analyze the design scheme of large-scale digital beamforming from the perspective of parallelism and multiplexing,while optimizing resources and errors.For FPGA implementation of elimination based on Cordic algorithm,the design details are described in detail and the module error and cancellation effect are tested.